.\" @(#)CodesignDemos	1.3 11/25/92 
.NA "CodesignDemos"
.SD
Demonstration of Hardware/Software Codesign using Ptolemy.
.SE
.LO "$PTOLEMY/src/domains/thor/demo"
.SV 1.3 11/25/92
.AL "Asawaree Kalavade"
.CO "1991 The Regents of the University of California"
.LD
This set of demos represents the use of ptolemy for hardware/software
codesign. Running these demos requires some proprietary Motorola code
which can not be supplied with the released code; so these demos should be
used to see what is possible - running them will fail.

Hardware/software codesign is the design methodology followed for the
design of mixed hardware/software systems where the partitioning of
the given algorithm into hardware and software implementations is delayed.
The software and hardware design processes are closely coupled - given an 
algorithm to be implemented in hardware and software, one can come up with 
a variety of hardware/software splits, develop, simulate, and verify the
designs, and then select the appropriate configuration with respect to cost 
and performance requirements.

The example case selected here is the design of a Telephone Channel
Simulator. A typical telephone channel generates impairments such
as linear and non-linear distortion, frequency offset and phase jitter,
and Gaussian noise. The algorithm for the channel simulator is described 
in the 
.c telephoneChannelAlg
demo. So the hardware/software codesign problem 
is one of designing a system corresponding to this algorithm - where the 
hardware consists of one or more programmable DSP chips and some custom logic,
and the software is the program running on these programmable processors.
Different multiprocessor configurations as well as system-level partitions
for this test case are demonstrated. The system is built using the 
SDF and the Thor domains.

.UH "Multiprocessor Configurations":
As a first cut, the algorithm is so partitioned that the DSPs execute
the entire algorithm in software. The hardware thus consists of the
two DSPs as well as A/D, D/A, and other glue logic, while the software is the
assembly code running on the two processors. 

.c SharedMem
The DSPs communicate using a shared memory between them. The various 
components of the design include the A/D and D/A blocks, glue logic,
and logic for generating appropriate clocks for the A/D and D/A blocks.
The A/D and D/A blocks are modeled functionally as SDF blocks nested
as Thor Wormholes. The A/D is abstracted as a transmit filter followed
by a quantizer. The stars BusToNum and NumToBus provide a conversion
between the integers sent/received by the SDF Domain and the logic-valued
Thor Domain. The interface between the data-driven SDF and the event-driven
Thor scheduler is taken care of by the trigger input to the signal generator 
galaxy. This trigger input data is used solely for the purpose of triggering
the wormhole for execution - the data itself is discarded. 
The full-duplex model consists of the signal from one end of the channel
being filtered, quantized, and send to the first DSP that impairs it.
The second DSP reads this data from the shared memory, and on completing
the impairments, sends it to the other end of the channel. Similar
processing is done on the signal from the other end of the channel.

.c SerialComm
This presents an alternative multiprocessor design where the two
DSPs communicate over their serial port instead. The signal from one
end of the channel is received by the first DSP, which impairs it 
and sends it over the serial port to the second DSP, which sends it
out to the other end of the channel. Meanwhile, a similar impairment
is carried out on the reverse direction for the signal transmitted
by the other DSP.
The hardware details are similar to the shared memory design.

The serial communication design has the advantage that it overcomes
the need for the expensive dual-ported memory needed by the shared memory 
design; however, it suffers from the drawback that is is not flexible 
in terms of code expansion (speed of serial communication places a
bound on the performance). The shared memory design is relatively
more flexible and can also support higher inter-DSP communication
throughput, though at an increased hardware cost. Also, communication
through the shared memory requires semaphore synchronization, this
imposes an additional burden on the software.

.UH "System-level design"
In order to reduce the cost of the design, an alternative design
possibility, using a single DSP, is also explored. Preliminary timing
analysis shows that one DSP cannot handle the computation load of the
bi-directional impairments of the full-duplex channel simulator. So,
computationally intensive blocks such as linear distortion and noise 
generation are possible candidates for migration from DSP software to 
custom hardware.

.c NoiseExt
As one alternative, the Gaussian noise generator is shifted to hardware
and is implemented by using special purpose diodes. This functional
migration provides sufficient computation cycles for a single DSP
to impair the signal in both directions.
The signals from two ends are multiplexed and sent to the DSP which
runs the impairment code. The impaired signals from the DSP are then routed
to the corresponding ends of the channel. For the purpose of simulation
the Gaussian noise generator is modeled as an SDF block. The output
Gaussian noise from this block superimposes the impaired signal, and
this noise signal is then passed to the D/A.

.c LinDisExt
Shifting much of the linear distortion block to hardware provides an other
design option. Much of the linear distortion imposed by a telephone
channel is due to switched-capacitor filters in codecs that provide
the interface to the digital network. By using similar codecs, we can
avoid having to replicate this distortion in software. The consequent
reduction in the filter order reduces the computation load of the DSP,
making it possible to develop yet another single processor design.

The tradeoffs in the use of special purpose hardware against programmable 
processors with respect to board space, component cost, and 
programmability can be compared and contrasted. The single DSP designs
are desirable for their low cost, as one processor is eliminated, 
but the price paid is loss of flexibility in changing these hardware
impairments.
.SA
telephoneChannelTest
.ES
