.\" @(#)CG56MultiSim_2	1.3 12/7/92 
.NA "CG56MultiSim_2"
.SD
This is a target architecture containing two Motorola DSP56000
processors, where the MultiSim-56000 target is used to generate the code
running on the two processors.
.SE
.LO "$PTOLEMY/src/domains/thor/demo"
.SV 1.3 12/7/92 
.AL "Asawaree Kalavade"
.CO "1992 The Regents of the University of California"
.LD
This describes a particular target architecture consisting of
two DSPs communicating with a shared dual-ported memory.
The key idea here is to use the CG56 domain to generate code
for the (two) processors in the system. The algorithm to be
implemented would have to specified in the CG56 domain, with
the target being set to MultiSim-56000. The target parameters can
be edited to reflect on the number of processors being used 
(2 in this case),
the location of the generated code files, etc. The parameters
of the DSP model can be set to appropriately specify the
location and name of the assembled code file for the particular
DSP. 
To be able to run this demo, the corresponding CG56 demo would have 
to be run first to generate the code. This demo can then be run so
that the processors execute the generated code.
Note: 
Running this demo requires some proprietary Motorola code
which can not be supplied with the released code; so running 
these demos would fail if you are outside UCBerkeley. 
.SA
MultiSim-56000
CG56 Demos
.ES

