Extraction of the chip netlist 
------------------------------

Routers are known to have bugs, so serious checks must be
made on the produced layout. To check the layout, we use
two ALLIANCE tools, lynx and lvx.

lynx is the ALLIANCE netlist extractor. From a physical layout it
extracts a netlist representation of the circuit. In our case,
we want to extract the core netlist.

lvx is the ALLIANCE netlist comparator. Its main function is to
check an extracted netlist with the original one, before any routing.

Hence, the design methodology is quite simple. We must extract
the core addaccu.ap with lynx and check the resulting netlist
with the original addaccu.vst file using lvx. As you will see,
lvx performs several other operations as a bonus.

Now, back to practice. You have to extract the layout using
lynx. Remember two things:
1) ALLIANCE tools deeply rely on appropriate
environment variables. For instance, you have to specify the
format the extracted netlist will be generated with.
2) extracted netlist files must be written in al format.

So you must:

> setenv MBK_OUT_LO al

to generate a extracted netlist file file called addaccu.al.

The actual execution of lynx is quite easy. Just type:

> lynx -v -f chip chip 
 
and you get your extracted netlist. Please notice that the first
chip stands for chip.ap and that second addaccu stands
for chip.al. One very important point is the -f option. It
instructs lynx to build the extracted netlist up to the standard-cells
level, ie the resulting netlist will exclusively contain cells
that belong to the standard-cells catalog. For more information please read 
the CATAL on-line documentation. The -v option stands for
"verbose". Extraction can be quite long on a big circuit, as any
good VLSI designer may know.
 
Press <return> to continue.
