#!/bin/csh -f

set ASIMUT = $TOP/bin/asimut
set GENLIB = $TOP/bin/genlib
set SCR    = $TOP/bin/scr
set RING   = $TOP/bin/ring
set LYNX   = $TOP/bin/lynx
set LVX    = $TOP/bin/lvx
set DESB   = $TOP/bin/desb
set PROOF  = $TOP/bin/proof
set DRUC   = $TOP/bin/druc
set S2R    = $TOP/bin/s2r

	# ###---------------------------------------------------------###
	#    cleaning generated files					#
	# ###---------------------------------------------------------###

/bin/rm -f *.al *.ap *.vst *.dsbr *.hns *.err *.lis *.deb *.fcf *.drc
/bin/rm -f result[123].pat chip.cif

	# ###---------------------------------------------------------###
	#    setting environnement variables				#
	# ###---------------------------------------------------------###

setenv MBK_CATA_LIB	.:$TOP/cells/scr:$TOP/cells/ring/pad12
setenv MBK_WORK_LIB	.

	# ###---------------------------------------------------------###
	#    check the correctness of specifications (Data-FLow VHDL)	#
	# running the logic simulation					#
	# ###---------------------------------------------------------###

$ASIMUT -b -c addaccu 
$ASIMUT -b addaccu addaccu result1  

	# ###---------------------------------------------------------###
	#    generate structural description (VHDL) of the circuit	#
	# ###---------------------------------------------------------###

setenv MBK_IN_LO vst 
setenv MBK_OUT_LO vst 
$GENLIB addaccu
$GENLIB chip

	# ###---------------------------------------------------------###
	#    check the correctness of the generated structural		#
	# description running the logic simulation			#
	# ###---------------------------------------------------------###

$ASIMUT chip addaccu result2

	# ###---------------------------------------------------------###
	#    place and route the circuit's core				#
	# ###---------------------------------------------------------###

setenv MBK_IN_PH ap
setenv MBK_OUT_PH ap
$SCR -p -r addaccu 

	# ###---------------------------------------------------------###
	#    place and route the circuit (core and pads)		#
	# ###---------------------------------------------------------###

$RING chip chip

	# ###---------------------------------------------------------###
	#    extract net-list from symbolic layout			#
	# ###---------------------------------------------------------###

setenv MBK_OUT_LO al 
setenv RDS_TECHNO_NAME	$TOP/etc/cmos_1.rds
$LYNX -v -f chip chip

	# ###---------------------------------------------------------###
	#    compare extracted net-list and structural description	#
	# ###---------------------------------------------------------###

$LVX vst al chip chip -f

	# ###---------------------------------------------------------###
	#    simulate the extracted net-list				#
	# ###---------------------------------------------------------###

setenv MBK_IN_LO al
$ASIMUT chip addaccu result2

	# ###---------------------------------------------------------###
	#    generate a Data-Flow description from the extracted	#
	# net-list							#
	# ###---------------------------------------------------------###

setenv DESB_TRACE_MODE 8
$DESB chip -i -v

	# ###---------------------------------------------------------###
	#    simulate the extracted data_flow description		#
	# ###---------------------------------------------------------###

$ASIMUT -b chip addaccu result3

	# ###---------------------------------------------------------###
	#    check the correctness of the extracted data_flow		#
	# description running the formal proover			#
	# ###----------------------------------------------------------##

$PROOF -d addaccu chip

	# ###---------------------------------------------------------###
	#    check design rules						#
	# ###---------------------------------------------------------###

$DRUC chip

	# ###---------------------------------------------------------###
	#    generates CIF description for 1.2 u process		#
	# ###---------------------------------------------------------###

setenv RDS_TECHNO_NAME	$TOP/etc/prol12.rds

setenv RDS_OUT cif 
setenv RDS_IN cif
$S2R -cv chip chip

exit
