      ******************************************************
      *   ANNOUNCEMENT OF ALLIANCE RELEASE 2.0   17 Feb 94 *
      ******************************************************

The release 2.0 of the public domain ALLIANCE VLSI/CAD system  is
now available at:

ftp.ibp.fr      [132.227.60.2]      in /ibp/softs/masi/alliance
cao-vlsi.ibp.fr [132.227.60.20]     in /pub/alliance

CONTENT

ALLIANCE is a complete set of CAD tools  and  portable  libraries
for  research and education in digital VLSI design.  The ALLIANCE
CAD  system has been developed at the MASI laboratory (Universite
Pierre et Marie Curie, Paris France). It includes a VHDL compiler
and simulator, logic synthesis tools, automatic place and  route,
DRC,  extractor,  functional  abstraction  and formal proof tools
etc...  All the ALLIANCE cell libraries  use  a  symbolic  layout
approach in  order  to provide process independence: Cmos process
from 1.6 micron to 0.8 micron have been successfully targetted.


Several new  tools and portable cell libraries have been introdu-
ced into release 2.0:

* Six parameterized portable CMOS generators:
  - RAGE static RAM generator
  - GROG high speed ROM generator
  - RSA  fast adder generator
  - BSG  barrel-shifter generator
  - AMG  pipelined multiplier generator
  - RFG  multi-ports register file generator

* A data-path compiler for high performance and high density cir-
  cuits (including a dedicated portable standard cell library)

* A Finite State Machine Synthesiser  SYF,  the  logic  synthesis
  tool  LOGIC  and  the  net-list  optimizer  NETOPTIM  allow the
  implementation of high complexity  controllers from VHDL input.

* A procedural layout debugger GENVIEW allows new  portable  gen-
  erators  or  custom blocks to be developed easily.  A new symb-
  olic layout editor GRAAL has a MOTIF interface.

INSTALLATION

ALLIANCE is totally free, under the terms of the GNU General Pub-
lic  License.  It includes C source files and on-line English do-
cumentation (UNIX man)

1) A hierarchical makefile allows each ALLIANCE tool to  be  com-
   piled and  installed separately.  The disk  space  required to
   compile  and  install  the full  ALLIANCE package is about 150
   megs.

2) The release 2.0 has been successfully compiled with K&R cc and
   GNU gcc compilers. The full alliance package can  now  run  on
   SPARC, LINUX and DEC architectures.

TUTORIALS

The release ALLIANCE 2.0 contains three separate tutorials:

1/ ADDACCU
   The  design  of a  very simple chip (adder/accumulator) to get
   started with the ALLIANCE tools (about 500 transistors).

2/ AMD2901
   The design of the 4 bits AMD2901 processor, from the VHDL spe-
   cification  to the  GDSII  layout, using the ALLIANCE portable
   standard cell library (about 3000 transistors).

3/ DLX
   The  design of the 32 bits DLX microprocessor (HENNESSY & PAT-
   TERSON) from the VHDL specification to the GDSII layout, using
   the  ALLIANCE  data-path  compiler  and  logic synthesis tools
   (about 30000 transistors).
