SPARK Simplifier Pro Edition


Reading round_6.fdl (for inherited FDL type declarations)
Processing round_6.vcg ...
Simplified VC: 1 - All conclusions proved
Simplified VC: 2 - All conclusions proved
Simplified VC: 3 - All conclusions proved
Simplified VC: 4 - All conclusions proved
Simplified VC: 5 - All conclusions proved
Simplified VC: 6 - All conclusions proved
Simplified VC: 7 - All conclusions proved
Simplified VC: 8 - All conclusions proved
Simplified VC: 9 - All conclusions proved
Simplified VC: 10 - All conclusions proved
Simplified VC: 11 - All conclusions proved
Simplified VC: 12 - All conclusions proved
Simplified VC: 13 - All conclusions proved
Simplified VC: 14 - All conclusions proved
Simplified VC: 15 - All conclusions proved
Simplified VC: 16 - All conclusions proved
Simplified VC: 17 - All conclusions proved
Simplified VC: 18 - All conclusions proved
Simplified VC: 19 - All conclusions proved
Simplified VC: 20 - All conclusions proved



Automatic simplification completed.

Simplified output sent to round_6.siv.
