****library: "sclib"
version: 5.7.4
aids: 12
aidname: user
aidname: io
aidname: compaction
aidname: pla
aidname: routing
aidname: silicon-compiler
variables: 3
SC_pwell_size[01,01500]: 15200
SC_vert_arc[015,01500]: mocmossub:Metal-2
SC_horiz_arc[015,01500]: mocmossub:Metal-1
aidname: vhdl-compiler
aidname: compensation
aidname: logeffort
aidname: network
aidname: drc
aidname: simulation
userbits: 6
techcount: 16
techname: generic lambda: 2000
techname: nmos lambda: 4000
techname: cmos lambda: 4000
techname: mocmos lambda: 2000
techname: mocmossub lambda: 400
techname: mocmos2 lambda: 2000
techname: bicmos lambda: 2000
techname: rcmos lambda: 2000
techname: cmosdodn lambda: 2000
techname: bipolar lambda: 4000
techname: schematic lambda: 4000
techname: fpga lambda: 2000
techname: pcb lambda: 2540000
techname: artwork lambda: 2000
techname: gem lambda: 2000
techname: efido lambda: 20000
view: schematic-page-1{p1}
view: layout{lay}
view: schematic{sch}
view: icon{ic}
view: documentation{doc}
view: compensated{comp}
view: skeleton{sk}
view: Verilog{ver}
view: VHDL{vhdl}
view: netlist{net}
view: netlist-als-format{net-als}
view: netlist-quisc-format{net-quisc}
view: netlist-silos-format{net-silos}
view: netlist-rsim-format{net-rsim}
view: netlist-netlisp-format{net-netlisp}
view: simulation-snapshot{sim}
view: unknown{}
cellcount: 15
maincell: 3
variables: 1
LIB_save_options[01,01500]: 32768
***cell: 0
name: and3{lay}
version: 2
creationdate: 902609292
revisiondate: 949951686
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aadirty: 2542
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