`line 1 "t/t_preproc_psl.v" 1
 


`line 4 "t/t_preproc_psl.v" 0
 
 

`line 7 "t/t_preproc_psl.v" 0
/*verilator metacomment preserved*/ 
 
/*verilator metacomment also_preserved*/ 

`line 11 "t/t_preproc_psl.v" 0
Hello in t_preproc_psl.v
    
    
    
    

`line 17 "t/t_preproc_psl.v" 0
    psl  default clock = (posedge clk);
    psl  fails1: cover {cyc==10};
    psl  assert always cyc!=10;
    psl  assert always cyc==3 -> mask==8'h2;
    psl  failsx: cover {cyc==3 && mask==8'h1};
     psl  fails2:
        cover {
	    cyc==3 && mask==8'h9};
         
	fails3: always assert {
	    cyc==3 && mask==8'h10 };
     
 29

`line 31 "t/t_preproc_psl.v" 0
    
    
   
  psl 
      fails_ml:
        assert always
  	    cyc==3 -> mask==8'h21;
    psl
      fails_mlalso:  assert always cyc==3 -> mask==8'h21;
     
 41

`line 43 "t/t_preproc_psl.v" 0
    psl  assert never (cyc==1 && reset_l);

`line 45 "t/t_preproc_psl.v" 0
    psl  fails3: assert always
    psl 	    cyc==3 -> mask==8'h21;
    

`line 49 "t/t_preproc_psl.v" 0
 
    psl  assert always
    psl        {[*]; cyc==3;
    psl         cyc==4; cyc==6};
    

`line 55 "t/t_preproc_psl.v" 0
 

`line 57 "t/t_preproc_psl.v" 0
 
      


`line 61 "t/t_preproc_psl.v" 0
 
 
    psl  assert always cyc!=10;

`line 65 "t/t_preproc_psl.v" 0
 
  `psl
psl assert always sig!=90;
  `verilog


`line 71 "t/t_preproc_psl.v" 0
 
72

`line 74 "t/t_preproc_psl.v" 2
