#!/bin/sh
# autopkgtest check: test_dff from README.md

set -e

WORKDIR=$(mktemp -d)
trap "rm -rf $WORKDIR" 0 INT QUIT ABRT PIPE TERM
cd $WORKDIR

cat > dff_tb.sv << 'EOF'
`timescale 1us/1us

module dff (
  input clk, d,
  output reg q
);

always @(posedge clk) begin
  q <= d;
end

endmodule


module dff_tb;
reg clk,d;
wire q;

dff udff (
  .clk(clk),
  .d(d),
  .q(q)
);
always  #10 clk <= !clk;

initial begin
  $dumpfile( "dump_dff" );
  $dumpvars( 0, dff_tb );

  clk = 0;
  @(negedge clk) d <= 1;
  @(negedge clk) d <= 1;
  @(negedge clk) d <= 0;
  @(negedge clk) d <= 0;
  @(negedge clk) d <= 1;
  repeat(3) @(posedge clk);
  $finish;
end

endmodule
EOF
cat > ref << 'EOF'

Covered covered-0.7.10 -- Verilog Code Coverage Utility
Written by Trevor Williams  (phase1geo@gmail.com)
Freely distributable under the GPL license

                            :::::::::::::::::::::::::::::::::::::::::::::::::::::
                            ::                                                 ::
                            ::  Covered -- Verilog Coverage Summarized Report  ::
                            ::                                                 ::
                            :::::::::::::::::::::::::::::::::::::::::::::::::::::


~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~   GENERAL INFORMATION   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
* Report generated from CDD file : test.cdd

* Reported by                    : Module

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~   LINE COVERAGE RESULTS   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Module/Task/Function      Filename                 Hit/ Miss/Total    Percent hit
---------------------------------------------------------------------------------------------------------------------
  $root                   NA                         0/    0/    0      100%
  dff_tb                  dff_tb.sv                  0/    0/    0      100%
  dff                     dff_tb.sv                  2/    0/    2      100%
---------------------------------------------------------------------------------------------------------------------
  Accumulated                                        2/    0/    2      100%


~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~   TOGGLE COVERAGE RESULTS   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
                                                           Toggle 0 -> 1                       Toggle 1 -> 0
Module/Task/Function      Filename                 Hit/ Miss/Total    Percent hit      Hit/ Miss/Total    Percent hit
---------------------------------------------------------------------------------------------------------------------
  $root                   NA                         0/    0/    0      100%             0/    0/    0      100%
  dff_tb                  dff_tb.sv                  3/    0/    3      100%             3/    0/    3      100%
  dff                     dff_tb.sv                  3/    0/    3      100%             3/    0/    3      100%
---------------------------------------------------------------------------------------------------------------------
  Accumulated                                        6/    0/    6      100%             6/    0/    6      100%


~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~   COMBINATIONAL LOGIC COVERAGE RESULTS   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
                                                                            Logic Combinations
Module/Task/Function                Filename                          Hit/Miss/Total    Percent hit
---------------------------------------------------------------------------------------------------------------------
  $root                             NA                                  0/   0/   0      100%
  dff_tb                            dff_tb.sv                           0/   0/   0      100%
  dff                               dff_tb.sv                           3/   0/   3      100%
---------------------------------------------------------------------------------------------------------------------
  Accumulated                                                           3/   0/   3      100%


~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~   FINITE STATE MACHINE COVERAGE RESULTS   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
                                                               State                             Arc
Module/Task/Function      Filename                Hit/Miss/Total    Percent Hit    Hit/Miss/Total    Percent hit
---------------------------------------------------------------------------------------------------------------------
  $root                   NA                        0/   0/   0      100%            0/   0/   0      100%
  dff_tb                  dff_tb.sv                 0/   0/   0      100%            0/   0/   0      100%
  dff                     dff_tb.sv                 0/   0/   0      100%            0/   0/   0      100%
---------------------------------------------------------------------------------------------------------------------
  Accumulated                                       0/   0/   0      100%            0/   0/   0      100%


EOF

# compile
iverilog dff_tb.sv
# create an empty CDD file for the design using covered's score command:
covered score -t dff_tb -v dff_tb.sv -o test.cdd -rS
# run simulation:
./a.out
# Fix the resulting vcd file:
sed -e '/^\$comment Show/d' -i dump_dff.vcd
# collect coverage data from resulting vcd:
covered score -cdd test.cdd -vcd dump_dff.vcd
# generate coverage report:
covered report test.cdd | diff ref -
