
/*
 *
 * Output of Kernel datastructure Unparser 
 *
 */

Basetype B   /*  "testin" ,  1  */ ;



 /*  "testin" ,  4  */ 
Atom	sreg	 :- (B &B &(B &B)) => (B &B);



 /*  "testin" ,  5  */ 
Atom	sbdff	 :- (B &B) => B;



 /*  "testin" ,  6  */ 
Atom	scount4	 :-  BOOL ->  BOOL ->  BOOL ->  BOOL ->  BOOL -> (B &B &B &B &B &B &(B &B &B &B)) => (B &B &(B &B &B &B));



 /*  "testin" ,  8  */ 
Atom	sbuffer	 :-  BOOL ->  BOOL -> B => (B &B);



 /*  "testin" ,  13  */ 
Atom	and	 :- (B &B) => B;



 /*  "testin" ,  14  */ 
Atom	nand	 :- (B &B) => B;



 /*  "testin" ,  15  */ 
Atom	or	 :- (B &B) => B;



 /*  "testin" ,  16  */ 
Atom	sxor	 :- (B &B) => B;



 /*  "testin" ,  17  */ 
Atom	nor	 :- (B &B) => B;



 /*  "testin" ,  18  */ 
Atom	not	 :- B => B;



 /*  "testin" ,  19  */ 
Atom	snor2	 :- (B &B) => B;



 /*  "testin" ,  20  */ 
Atom	snor3	 :- (B &B &B) => B;



 /*  "testin" ,  21  */ 
Atom	snand2	 :- (B &B) => B;



 /*  "testin" ,  22  */ 
Atom	sfix	 :-  <>  => (B &B);



 /*  "testin" ,  25  */ 
Atom	sipad	 :-  <>  => B;



 /*  "testin" ,  26  */ 
Atom	sopad	 :- [B];



 /*  "testin" ,  29  */ 
Def	regpart1 :- (B &B &B &B &B) => (B &B);
   	regpart1 [ck_32,reset_33,d2_34,d1_35,d0_36] = (sreg   [ck_32, reset_33,  [d0_36, d1_35]]);



 /*  "testin" ,  33  */ 
Def	fsmlog1 :- (B &B &B &B) => (B &B &B &B &B &B);
   	fsmlog1 [q2_47,q0_48,tp_49,ip_50] = 
  ( [srdata1_54, srdata0_53, timeout_52, d1_55, d0_56, newclock_51]
  Where
   newclock_51 = (and   [(not  q0_48), q2_47]);
   timeout_52 = (and   [(not  q0_48), (not  q2_47)]);
   srdata0_53 = (and   [q0_48, (not  q2_47)]);
   srdata1_54 = (and   [q0_48, q2_47]);
   d1_55 = (or   [ip_50, (and   [(not  tp_49), q2_47])]);
   d0_56 = (or   [(and   [ip_50, (and   [(not  q0_48), q2_47])]), (or   [(and   [tp_49, (and   [(not  q0_48), q2_47])]), (and   [(not  ip_50), (and   [(not  tp_49), q0_48])])])])
  EndWhere) 
  ;



 /*  "testin" ,  49  */ 
Def	fsm :- (B &B &B &B) => (B &B &(B &B));
   	fsm [ck_71,reset_72,tp_73,ip_74] = 
  ( [timeout_78, newclock_81, srdata_75]
  Where
   srdata_75 =  [srdata0_76, srdata1_77];
    [srdata1_77, srdata0_76, timeout_78, d1_79, d0_80, newclock_81] = (fsmlog1  [q2_82, q0_83, tp_73, ip_74]);
    [q2_82, q0_83] = (regpart1  [ck_71, reset_72, x_84, d1_79, d0_80])
  EndWhere) 
  ;



 /*  "testin" ,  59  */ 
Def	ldff :- (B &B &B) => B;
   	ldff [ld_90,ck_91,d_92] = 
  (q_93
  Where
   q_93 = (sbdff   [ck_91, ddff_94]);
   ddff_94 = (nand   [(nand   [(not  ld_90), q_93]), (nand   [ld_90, d_92])])
  EndWhere) 
  ;



 /*  "testin" ,  68  */ 
Def	posedge :- (B &B) => B;
   	posedge [ck_98,in_99] = 
  (out_100
  Where
   out_100 = (and   [(not  (sbdff   [ck_98, in_99])), in_99])
  EndWhere) 
  ;



 /*  "testin" ,  76  */ 
Def	edge :- (B &B) => B;
   	edge [ck_104,in_105] = 
  ((sxor   [(sbdff   [ck_104, q_106]), q_106])
  Where
   q_106 = (sbdff   [ck_104, in_105])
  EndWhere) 
  ;



 /*  "testin" ,  84  */ 
Def	timer :- (B &B &B) => B;
   	timer [ck_124,reset_125,r_126] = 
  (tp_127
  Where
   tp_127 = (snor2   [(snor2   [q2_128, q3_129]), (snand2   [q0_130, (not  q1_131)])]);
    [q0_130, q1_131, q2_128, q3_129] = q_132;
    [cu_133, cd_134, q_132] = (scount4 False  True  True  False  False   [d1_135, reset_125, ck_124, d2_136, one_137, d3_138, d4_139]);
    [zero_140, one_137] = (sfix   [])
  EndWhere) 
  ;



 /*  "testin" ,  96  */ 
Def	srff :- (B &B &B &B) => B;
   	srff [ck_146,reset_147,s_148,r_149] = 
  (q_150
  Where
   q_150 = (sbdff   [ck_146, (snor3   [reset_147, r_149, (snor2   [s_148, q_150])])])
  EndWhere) 
  ;



 /*  "testin" ,  107  */ 
Def	core :- (B &B &B) => (B &B &B &B);
   	core [ck_166,cd_167,reset_168] = 
  ( [timeout_180, syncclk_170, dataout_172, syncdata_169]
  Where
   syncdata_169 = (ldff  [syncclk_170, ckbuf0_171, dataout_172]);
    [ckbuf0_171, ckbuf1_173] = ckbuf_174;
   ckbuf_174 = (sbuffer False  True  ck_166);
   dataout_172 = (srff  [ckbuf0_171, reset_168, srdata1_175, srdata0_176]);
   syncclk_170 = (posedge  [ckbuf0_171, newclock_177]);
   ip_178 = (edge  [ckbuf0_171, cd_167]);
    [srdata0_176, srdata1_175] = srdata_179;
    [timeout_180, newclock_177, srdata_179] = (fsm  [ckbuf0_171, reset_168, (timer  [ckbuf0_171, reset_168, ip_178]), ip_178])
  EndWhere) 
  ;



 /*  "testin" ,  126  */ 
Def	chip :- [ <> ];
   	chip dc_189 = 
  (
  { sopad  timeout_190,
   sopad  syncclk_191,
   sopad  dataout_192,
   sopad  syncdata_193
  } 
  Where
    [timeout_190, syncclk_191, dataout_192, syncdata_193] = (core  [ck_194, cd_195, reset_196]);
   ck_194 = (sipad   []);
   cd_195 = (sipad   []);
   reset_196 = (sipad   [])
  EndWhere) 
  

