;; Copyright (C) 2026 Free Software Foundation, Inc.
;;
;; This file is part of GCC.
;;
;; GCC is free software; you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
;; the Free Software Foundation; either version 3, or (at your option)
;; any later version.
;;
;; GCC is distributed in the hope that it will be useful,
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
;; GNU General Public License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3.  If not see
;; <http://www.gnu.org/licenses/>.
;;

;; HYGON c86-4g-m7/m8 Scheduling
;; Modeling automatons for decoders, integer execution pipes,
;; AGU pipes, branch, floating point execution, fp store units,
;; integer and floating point dividers.  Split fpu1 and fpu3
;; into their own automata to keep these units independent
;; without increasing the main c86_4g_m7_fpu state space.
(define_automaton "c86_4g_m7, c86_4g_m7_ieu, c86_4g_m7_agu, c86_4g_m7_fpu02, c86_4g_m7_fpu13, c86_4g_m7_idiv, c86_4g_m7_fdiv")

;; Decoders unit has 4 decoders and all of them can decode fast path
;; and vector type instructions.
(define_cpu_unit "c86-4g-m7-decode0" "c86_4g_m7")
(define_cpu_unit "c86-4g-m7-decode1" "c86_4g_m7")
(define_cpu_unit "c86-4g-m7-decode2" "c86_4g_m7")
(define_cpu_unit "c86-4g-m7-decode3" "c86_4g_m7")

;; Currently blocking all decoders for vector path instructions as
;; they are dispatched separetely as microcode sequence.
(define_reservation "c86-4g-m7-vector" "c86-4g-m7-decode0+c86-4g-m7-decode1+c86-4g-m7-decode2+c86-4g-m7-decode3")

;; Direct instructions can be issued to any of the four decoders.
(define_reservation "c86-4g-m7-direct" "c86-4g-m7-decode0|c86-4g-m7-decode1|c86-4g-m7-decode2|c86-4g-m7-decode3")

;; Fix me: Need to revisit this later to simulate fast path double behavior.
(define_reservation "c86-4g-m7-double" "c86-4g-m7-direct")

;; Integer unit 4 ALU pipes.
(define_cpu_unit "c86-4g-m7-ieu0" "c86_4g_m7_ieu")
(define_cpu_unit "c86-4g-m7-ieu1" "c86_4g_m7_ieu")
(define_cpu_unit "c86-4g-m7-ieu2" "c86_4g_m7_ieu")
(define_cpu_unit "c86-4g-m7-ieu3" "c86_4g_m7_ieu")

;; One separated integer divider.
(define_cpu_unit "c86-4g-m7-idiv" "c86_4g_m7_idiv")

;; c86-4g-m7 has an additional branch unit.
(define_cpu_unit "c86-4g-m7-bru0" "c86_4g_m7_ieu")
(define_reservation "c86-4g-m7-ieu" "c86-4g-m7-ieu0|c86-4g-m7-ieu1|c86-4g-m7-ieu2|c86-4g-m7-ieu3")

;; 3 AGU pipes in c86-4g-m7
(define_cpu_unit "c86-4g-m7-agu0" "c86_4g_m7_agu")
(define_cpu_unit "c86-4g-m7-agu1" "c86_4g_m7_agu")
(define_cpu_unit "c86-4g-m7-agu2" "c86_4g_m7_agu")
(define_reservation "c86-4g-m7-agu-reserve" "c86-4g-m7-agu0|c86-4g-m7-agu1|c86-4g-m7-agu2")

;; Load is 4 cycles.  We do not model reservation of load unit.
(define_reservation "c86-4g-m7-load" "c86-4g-m7-agu-reserve")
(define_reservation "c86-4g-m7-store" "c86-4g-m7-agu-reserve")

;; vectorpath (microcoded) instructions are single issue instructions.
;; So, they occupy all the integer units.
(define_reservation "c86-4g-m7-ivector" "c86-4g-m7-ieu0+c86-4g-m7-ieu1
					 +c86-4g-m7-ieu2+c86-4g-m7-ieu3+c86-4g-m7-bru0
					 +c86-4g-m7-agu0+c86-4g-m7-agu1+c86-4g-m7-agu2")

;; Floating point unit 4 FP pipes.
(define_cpu_unit "c86-4g-m7-fpu0" "c86_4g_m7_fpu02")
(define_cpu_unit "c86-4g-m7-fpu1" "c86_4g_m7_fpu13")
(define_cpu_unit "c86-4g-m7-fpu2" "c86_4g_m7_fpu02")
(define_cpu_unit "c86-4g-m7-fpu3" "c86_4g_m7_fpu13")

(define_reservation "c86-4g-m7-fpu" "c86-4g-m7-fpu0|c86-4g-m7-fpu1|c86-4g-m7-fpu2|c86-4g-m7-fpu3")
(define_reservation "c86-4g-m7-fpu_0_1" "c86-4g-m7-fpu0|c86-4g-m7-fpu1")
(define_reservation "c86-4g-m7-fpu_0_2" "c86-4g-m7-fpu0|c86-4g-m7-fpu2")
(define_reservation "c86-4g-m7-fpu_0_2x2" "c86-4g-m7-fpu0*2|c86-4g-m7-fpu2*2")
(define_reservation "c86-4g-m7-fpu_0_2x4" "c86-4g-m7-fpu0*4|c86-4g-m7-fpu2*4")
(define_reservation "c86-4g-m7-fpu_0_3" "c86-4g-m7-fpu0|c86-4g-m7-fpu3")
(define_reservation "c86-4g-m7-fpu_1_3" "c86-4g-m7-fpu1|c86-4g-m7-fpu3")
(define_reservation "c86-4g-m7-fpu_1_3x2" "c86-4g-m7-fpu1*2|c86-4g-m7-fpu3*2")
(define_reservation "c86-4g-m7-fpu_1_3x3" "c86-4g-m7-fpu1*3|c86-4g-m7-fpu3*3")
(define_reservation "c86-4g-m7-fpu_1_3x6" "c86-4g-m7-fpu1*6|c86-4g-m7-fpu3*6")
(define_reservation "c86-4g-m7-fpux2" "c86-4g-m7-fpu0*2|c86-4g-m7-fpu1*2|c86-4g-m7-fpu2*2|c86-4g-m7-fpu3*2")
(define_reservation "c86-4g-m7-fpux4" "c86-4g-m7-fpu0*4|c86-4g-m7-fpu1*4|c86-4g-m7-fpu2*4|c86-4g-m7-fpu3*4")
(define_reservation "c86-4g-m7-fpux8" "c86-4g-m7-fpu0*8|c86-4g-m7-fpu1*8|c86-4g-m7-fpu2*8|c86-4g-m7-fpu3*8")
(define_reservation "c86-4g-m7-fpux6" "c86-4g-m7-fpu0*6|c86-4g-m7-fpu1*6|c86-4g-m7-fpu2*6|c86-4g-m7-fpu3*6")
(define_reservation "c86-4g-m7-fpux16" "c86-4g-m7-fpu0*16|c86-4g-m7-fpu1*16|c86-4g-m7-fpu2*16|c86-4g-m7-fpu3*16")
(define_reservation "c86-4g-m7-fvector" "c86-4g-m7-fpu0+c86-4g-m7-fpu1
					 +c86-4g-m7-fpu2+c86-4g-m7-fpu3
					 +c86-4g-m7-agu0+c86-4g-m7-agu1+c86-4g-m7-agu2")

;; Two FP dividers.
(define_cpu_unit "c86-4g-m7-fdiv1" "c86_4g_m7_fdiv")
(define_cpu_unit "c86-4g-m7-fdiv3" "c86_4g_m7_fdiv")

(define_reservation "c86-4g-m7-fp1fdiv1x4" "(c86-4g-m7-fpu1+c86-4g-m7-fdiv1)*4")
(define_reservation "c86-4g-m7-fp3fdiv3x4" "(c86-4g-m7-fpu3+c86-4g-m7-fdiv3)*4")
(define_reservation "c86-4g-m7-fdiv13" "(c86-4g-m7-fdiv1+c86-4g-m7-fdiv3)")
(define_reservation "c86-4g-m7-fp13div13" "(c86-4g-m7-fpu1+c86-4g-m7-fpu3+c86-4g-m7-fdiv1+c86-4g-m7-fdiv3)")
(define_reservation "c86-4g-m7-fp13div13x4" "c86-4g-m7-fp13div13*4")
(define_reservation "c86-4g-m7-fp1div1_fp3div3_x4x8" "(c86-4g-m7-fp1fdiv1x4,c86-4g-m7-fdiv1*8)|(c86-4g-m7-fp3fdiv3x4,c86-4g-m7-fdiv3*8)")
(define_reservation "c86-4g-m7-fp1div1_fp3div3_x4x9" "(c86-4g-m7-fp1fdiv1x4,c86-4g-m7-fdiv1*9)|(c86-4g-m7-fp3fdiv3x4,c86-4g-m7-fdiv3*9)")
(define_reservation "c86-4g-m7-fp1div1_fp3div3_x4x11" "(c86-4g-m7-fp1fdiv1x4,c86-4g-m7-fdiv1*11)|(c86-4g-m7-fp3fdiv3x4,c86-4g-m7-fdiv3*11)")
(define_reservation "c86-4g-m7-fp1div1_fp3div3_x4x15" "(c86-4g-m7-fp1fdiv1x4,c86-4g-m7-fdiv1*15)|(c86-4g-m7-fp3fdiv3x4,c86-4g-m7-fdiv3*15)")
(define_reservation "c86-4g-m7-fp1div1_fp3div3_x4x18" "(c86-4g-m7-fp1fdiv1x4,c86-4g-m7-fdiv1*18)|(c86-4g-m7-fp3fdiv3x4,c86-4g-m7-fdiv3*18)")

;; IMOV/IMOVX

;; Some reservations keep the historical "m7" naming, while their CPU
;; attributes include both m7 and m8.
(define_insn_reservation "c86_4g_m7_imov_xchg" 1
			(and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			     (and (eq_attr "type" "imov")
				  (and (eq_attr "c86_decode" "vector")
				       (eq_attr "memory" "none"))))
			 "c86-4g-m7-vector")

(define_insn_reservation "c86_4g_m7_imov_xchg_load" 5
			(and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			     (and (eq_attr "type" "imov")
				  (and (eq_attr "c86_decode" "vector")
				       (eq_attr "memory" "!none"))))
			 "c86-4g-m7-vector,c86-4g-m7-load")

(define_insn_reservation "c86_4g_m7_imovx_cwde" 2
			(and (eq_attr "cpu" "c86_4g_m7")
			     (and (eq_attr "type" "imovx")
				  (and (eq_attr "c86_decode" "double")
				       (eq_attr "memory" "none"))))
			 "c86-4g-m7-direct,c86-4g-m7-ieu")

(define_insn_reservation "c86_4g_m8_imovx_cwde" 1
			(and (eq_attr "cpu" "c86_4g_m8")
			     (and (eq_attr "type" "imovx")
				  (and (eq_attr "c86_decode" "double")
				       (eq_attr "memory" "none"))))
			 "c86-4g-m7-direct,c86-4g-m7-ieu")

(define_insn_reservation "c86_4g_m7_imov" 1
			(and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			     (and (eq_attr "type" "imov,imovx")
				  (and (eq_attr "c86_decode" "direct")
				       (eq_attr "memory" "none"))))
	     "c86-4g-m7-direct,c86-4g-m7-ieu")

(define_insn_reservation "c86_4g_m7_imov_load" 5
			(and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			     (and (eq_attr "type" "imov,imovx")
				  (and (eq_attr "c86_decode" "!vector")
				       (eq_attr "memory" "load"))))
			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-ieu")

(define_insn_reservation "c86_4g_m7_imov_store" 1
			(and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			     (and (eq_attr "type" "imov,imovx")
				  (and (eq_attr "c86_decode" "!vector")
				       (eq_attr "memory" "store"))))
			 "c86-4g-m7-direct,c86-4g-m7-store,c86-4g-m7-ieu")

;; PUSH
(define_insn_reservation "c86_4g_m7_push" 1
			(and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			     (and (eq_attr "type" "push,sse")
				  (eq_attr "memory" "store")))
			 "c86-4g-m7-direct,c86-4g-m7-store")

(define_insn_reservation "c86_4g_m7_push_mem" 5
			(and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
				 (and (eq_attr "type" "push")
				  (eq_attr "memory" "both")))
			 "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-store")

;; POP
(define_insn_reservation "c86_4g_m7_pop" 4
			(and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			     (and (eq_attr "type" "pop")
				  (eq_attr "memory" "load")))
			 "c86-4g-m7-direct,c86-4g-m7-load")

(define_insn_reservation "c86_4g_m7_pop_mem" 5
	    (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
		 (and (eq_attr "type" "pop")
		  (eq_attr "memory" "both")))
	     "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-store")

;; IMUL/IMULX
(define_insn_reservation "c86_4g_m7_imul" 3
			(and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			     (and (eq_attr "type" "imul,imulx")
				  (eq_attr "memory" "none")))
			 "c86-4g-m7-direct,c86-4g-m7-ieu1")

(define_insn_reservation "c86_4g_m7_imul_load" 7
			(and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			     (and (eq_attr "type" "imul")
				  (eq_attr "memory" "!none")))
			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-ieu1")

;; IDIV
(define_insn_reservation "c86_4g_m7_idiv" 7
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "idiv")
				   (and (eq_attr "mode" "!QI")
					(eq_attr "memory" "none"))))
			 "c86-4g-m7-double,c86-4g-m7-ieu3,c86-4g-m7-idiv*7")

(define_insn_reservation "c86_4g_m7_idiv_QI" 6
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "idiv")
				   (and (eq_attr "mode" "QI")
					(eq_attr "memory" "none"))))
			 "c86-4g-m7-double,c86-4g-m7-ieu3,c86-4g-m7-idiv*6")

(define_insn_reservation "c86_4g_m7_idiv_load" 11
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "idiv")
				   (and (eq_attr "mode" "!QI")
					(eq_attr "memory" "load"))))
			 "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-ieu3,c86-4g-m7-idiv*7")

(define_insn_reservation "c86_4g_m7_idiv_QI_load" 10
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "idiv")
				   (and (eq_attr "mode" "QI")
					(eq_attr "memory" "load"))))
			 "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-ieu3,c86-4g-m7-idiv*6")

;; Integer/genaral Instructions
(define_insn_reservation "c86_4g_m7_insn" 1
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "alu,negnot,rotate1,ishift1,test,incdec,icmp,
						    rotate,rotatex,ishift,ishiftx,icmov")
				   (eq_attr "memory" "none,unknown")))
			 "c86-4g-m7-direct,c86-4g-m7-ieu")

(define_insn_reservation "c86_4g_m7_insn_load" 5
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "alu,incdec,icmp,test,ishift,
						    ishiftx,icmov,rotate,rotatex")
				   (eq_attr "memory" "load")))
			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-ieu")

(define_insn_reservation "c86_4g_m7_insn_store" 1
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "ishift1,rotate1,rotate,incdec,
						    alu,icmov,ishift,negnot,alu1")
				   (eq_attr "memory" "store")))
			 "c86-4g-m7-direct,c86-4g-m7-ieu,c86-4g-m7-store")

(define_insn_reservation "c86_4g_m7_insn2_store" 5
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "icmp")
				   (eq_attr "memory" "store")))
			 "c86-4g-m7-direct,c86-4g-m7-ieu,c86-4g-m7-store")

(define_insn_reservation "c86_4g_m7_insn_both" 5
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "alu,negnot,rotate1,ishift1,incdec,rotate,
						    rotatex,ishift,ishiftx,icmov")
				   (eq_attr "memory" "both")))
			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-ieu,c86-4g-m7-store")

(define_insn_reservation "c86_4g_m7_setcc" 1
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "setcc")
				   (eq_attr "memory" "none,unknown")))
			 "c86-4g-m7-direct,c86-4g-m7-ieu0|c86-4g-m7-ieu3")

(define_insn_reservation "c86_4g_m7_setcc_load" 5
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "setcc")
				   (eq_attr "memory" "load")))
			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-ieu0|c86-4g-m7-ieu3")

(define_insn_reservation "c86_4g_m7_setcc_store" 1
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "setcc")
				   (eq_attr "memory" "store")))
			 "c86-4g-m7-direct,c86-4g-m7-store,c86-4g-m7-ieu0|c86-4g-m7-ieu3")

;; ALU1
(define_insn_reservation "c86_4g_m7_alu1_double" 2
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "alu1")
				   (and (eq_attr "c86_decode" "double")
					(eq_attr "memory" "none,unknown"))))
			 "c86-4g-m7-double,c86-4g-m7-ieu")

(define_insn_reservation "c86_4g_m7_alu1_double_load" 6
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "alu1")
				   (and (eq_attr "c86_decode" "double")
					(eq_attr "memory" "both"))))
			 "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-store,c86-4g-m7-ieu")

(define_insn_reservation "c86_4g_m7_alu1_vector" 3
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "alu1")
				   (and (eq_attr "c86_decode" "vector")
					(eq_attr "memory" "none,unknown"))))
			 "c86-4g-m7-vector,c86-4g-m7-ivector*3")

(define_insn_reservation "c86_4g_m7_alu1_vector_load" 7
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "alu1")
				   (and (eq_attr "c86_decode" "vector")
					(eq_attr "memory" "both"))))
			 "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-store,c86-4g-m7-ivector*3")

(define_insn_reservation "c86_4g_m7_alu1_direct" 1
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "alu1")
				   (and (eq_attr "c86_decode" "direct")
					(eq_attr "memory" "none,unknown"))))
			 "c86-4g-m7-direct,c86-4g-m7-ieu")

(define_insn_reservation "c86_4g_m7_alu1_direct_load" 5
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "alu1")
				   (and (eq_attr "c86_decode" "direct")
					(eq_attr "memory" "both"))))
			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-store,c86-4g-m7-ieu")

;; CALL/CALLV
(define_insn_reservation "c86_4g_m7_call" 1
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (eq_attr "type" "call,callv"))
			 "c86-4g-m7-double,c86-4g-m7-store,c86-4g-m7-bru0")

;; IBR
(define_insn_reservation "c86_4g_m7_branch" 1
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "ibr")
				   (eq_attr "memory" "none")))
			  "c86-4g-m7-direct,c86-4g-m7-bru0")

(define_insn_reservation "c86_4g_m7_branch_load" 5
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "ibr")
				   (eq_attr "memory" "load")))
			  "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-bru0")

;; LEA
(define_insn_reservation "c86_4g_m7_lea" 1
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (eq_attr "type" "lea"))
			 "c86-4g-m7-direct,c86-4g-m7-ieu")

;; LEAVE
(define_insn_reservation "c86_4g_m7_leave" 1
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (eq_attr "type" "leave"))
			 "c86-4g-m7-double,c86-4g-m7-ieu,c86-4g-m7-store")

;; STR
(define_insn_reservation "c86_4g_m7_str" 3
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "str")
				   (eq_attr "memory" "none")))
			 "c86-4g-m7-vector,c86-4g-m7-ivector*3")

(define_insn_reservation "c86_4g_m7_str_load" 7
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "str")
				   (eq_attr "memory" "load")))
			 "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-ivector*3")


(define_insn_reservation "c86_4g_m7_ieu_vector" 5
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "other,multi")
				   (and (eq_attr "unit" "!i387")
				       (eq_attr "memory" "none,unknown"))))
			 "c86-4g-m7-vector,c86-4g-m7-ivector*5")

(define_insn_reservation "c86_4g_m7_ieu_vector_load" 9
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "other,multi")
				   (and (eq_attr "unit" "!i387")
					(eq_attr "memory" "load"))))
			 "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-ivector*5")

;; SSEINS
(define_insn_reservation "c86_4g_m7_sse_insertimm" 3
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sseins")
				   (and (eq_attr "memory" "none")
					(eq_attr "length_immediate" "2"))))
			 "c86-4g-m7-double,c86-4g-m7-fpu_0_3,c86-4g-m7-fpu1")

(define_insn_reservation "c86_4g_m7_sse_insert" 3
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sseins")
				   (and (eq_attr "memory" "none")
					(eq_attr "length_immediate" "!2"))))
			 "c86-4g-m7-direct,c86-4g-m7-fpu1*2")

;; FCMOV
(define_insn_reservation "c86_4g_m7_fp_cmov" 4
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (eq_attr "type" "fcmov"))
			 "c86-4g-m7-vector,c86-4g-m7-fvector*3")

;; FLD
(define_insn_reservation "c86_4g_m7_fp_mov_direct_load" 8
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "c86_decode" "direct")
				   (and (eq_attr "type" "fmov")
					(eq_attr "memory" "load"))))
			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu1")

;; FST
(define_insn_reservation "c86_4g_m7_fp_mov_direct_store" 8
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "c86_decode" "direct")
				   (and (eq_attr "type" "fmov")
					(eq_attr "memory" "store"))))
			 "c86-4g-m7-direct,c86-4g-m7-fpu1,c86-4g-m7-store")

;; FILD
(define_insn_reservation "c86_4g_m7_fp_mov_double_load" 11
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "c86_decode" "double")
				   (and (eq_attr "type" "fmov")
					(eq_attr "memory" "load"))))
			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu1")

;; FIST
(define_insn_reservation "c86_4g_m7_fp_mov_double_store" 8
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "c86_decode" "double")
				   (and (eq_attr "type" "fmov")
					(eq_attr "memory" "store"))))
			 "c86-4g-m7-double,c86-4g-m7-fpu1,c86-4g-m7-store")

(define_insn_reservation "c86_4g_m7_fp_mov_direct" 1
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "c86_decode" "direct")
				   (and (eq_attr "type" "fmov")
					(eq_attr "memory" "none"))))
			 "c86-4g-m7-direct,c86-4g-m7-fpu1")

;; FSQRT
(define_insn_reservation "c86_4g_m7_fp_sqrt" 22
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "fpspc")
				   (eq_attr "c86_attr" "sqrt")))
			 "c86-4g-m7-direct,c86-4g-m7-fp1div1_fp3div3_x4x18")

;; FPSPC
(define_insn_reservation "c86_4g_m7_fp_spc_direct" 5
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "fpspc")
				   (and (eq_attr "c86_decode" "direct")
				    (and (eq_attr "c86_attr" "other")
					 (eq_attr "memory" "store")))))
			 "c86-4g-m7-direct,c86-4g-m7-store,c86-4g-m7-fpu3")

(define_insn_reservation "c86_4g_m7_fp_spc" 6
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "fpspc")
				   (and (eq_attr "c86_attr" "other")
					(eq_attr "memory" "none"))))
			 "c86-4g-m7-vector,c86-4g-m7-fvector*6")

(define_insn_reservation "c86_4g_m7_fp_op_mul" 5
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "fop,fmul")
				   (eq_attr "memory" "none")))
			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_2")

(define_insn_reservation "c86_4g_m7_fp_op_mul_load" 12
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "fop,fmul")
				   (and (eq_attr "fp_int_src" "false")
					(eq_attr "memory" "load"))))
			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2")

(define_insn_reservation "c86_4g_m7_fp_op_imul_load" 16
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "fmul")
				   (and (eq_attr "fp_int_src" "true")
					(eq_attr "memory" "!none"))))
			"c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu0,c86-4g-m7-fpu_0_2")

;; FDIV
(define_insn_reservation "c86_4g_m7_fp_div" 15
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "fdiv")
				   (eq_attr "memory" "none")))
			 "c86-4g-m7-direct,c86-4g-m7-fp1div1_fp3div3_x4x11")

(define_insn_reservation "c86_4g_m7_fp_div_load" 22
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "fdiv")
				   (and (eq_attr "fp_int_src" "false")
					(eq_attr "memory" "!none"))))
			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fp1div1_fp3div3_x4x11")

(define_insn_reservation "c86_4g_m7_fp_idiv_load" 26
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "fdiv")
				   (and (eq_attr "fp_int_src" "true")
					(eq_attr "memory" "!none"))))
			 "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu1*4,c86-4g-m7-fp1div1_fp3div3_x4x11")

(define_insn_reservation "c86_4g_m7_fp_fsgn" 1
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (eq_attr "type" "fsgn"))
			 "c86-4g-m7-direct,c86-4g-m7-fpu_1_3")

;; FCMP
(define_insn_reservation "c86_4g_m7_fp_fcmp" 5
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "fcmp")
				   (eq_attr "memory" "none")))
			 "c86-4g-m7-double,c86-4g-m7-fpu0,c86-4g-m7-fpu1")

(define_insn_reservation "c86_4g_m7_fp_fcmp_load" 12
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "fcmp")
				   (eq_attr "memory" "load")))
			 "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu0,c86-4g-m7-fpu1")

;; MMX
(define_insn_reservation "c86_4g_m7_fp_mmx" 1
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (eq_attr "type" "mmx"))
			 "c86-4g-m7-direct")

(define_insn_reservation "c86_4g_m7_mmx_add_cmp" 1
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "mmxadd,mmxcmp")
				   (eq_attr "memory" "none")))
			 "c86-4g-m7-direct,c86-4g-m7-fpu")

(define_insn_reservation "c86_4g_m7_mmx_add_cmp_load" 8
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "mmxadd,mmxcmp")
				   (eq_attr "memory" "load")))
			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu")

(define_insn_reservation "c86_4g_m7_mmx_cvt" 1
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "mmxcvt")
				   (and (eq_attr "c86_attr" "other")
					(eq_attr "memory" "none"))))
			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_1")

(define_insn_reservation "c86_4g_m7_mmx_cvt_load" 8
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "mmxcvt")
				   (and (eq_attr "c86_attr" "other")
					(eq_attr "memory" "load"))))
			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_1")

(define_insn_reservation "c86_4g_m7_mmx_shift" 1
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "mmxshft")
				   (and (eq_attr "c86_attr" "other")
					(eq_attr "memory" "none"))))
			 "c86-4g-m7-direct,c86-4g-m7-fpu1")

(define_insn_reservation "c86_4g_m7_mmx_shift_load" 8
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "mmxshft")
				   (and (eq_attr "c86_attr" "other")
					(eq_attr "memory" "load"))))
			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu1")

(define_insn_reservation "c86_4g_m7_mmx_shift_avg" 1
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "mmxshft")
				   (and (eq_attr "c86_attr" "avg")
					(eq_attr "memory" "none"))))
			 "c86-4g-m7-direct,c86-4g-m7-fpu")

(define_insn_reservation "c86_4g_m7_mmx_shift_avg_load" 8
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "mmxshft")
				   (and (eq_attr "c86_attr" "avg")
					(eq_attr "memory" "load"))))
			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu")

;; SADBW
(define_insn_reservation "c86_4g_m7_mmx_shift_sadbw" 3
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "mmxshft")
				   (and (eq_attr "c86_attr" "sadbw")
					(eq_attr "memory" "none"))))
			 "c86-4g-m7-direct,c86-4g-m7-fpu0")

(define_insn_reservation "c86_4g_m7_mmx_shift_sadbw_load" 10
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "mmxshft")
				   (and (eq_attr "c86_attr" "sadbw")
					(eq_attr "memory" "load"))))
			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu0")

(define_insn_reservation "c86_4g_m7_mmx_mov" 4
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "mmxmov")
				   (eq_attr "memory" "none")))
			 "c86-4g-m7-direct,c86-4g-m7-fpu1")

(define_insn_reservation "c86_4g_m7_mmx_mov_store" 4
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "mmxmov")
				   (and (eq_attr "c86_attr" "other")
					(eq_attr "memory" "store"))))
			 "c86-4g-m7-direct,c86-4g-m7-store,c86-4g-m7-fpu1")

(define_insn_reservation "c86_4g_m7_mmx_mov_load" 11
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "mmxmov")
				   (eq_attr "memory" "load")))
			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu1")

(define_insn_reservation "c86_4g_m7_mmx_mul" 3
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "mmxmul")
				   (eq_attr "memory" "none")))
			  "c86-4g-m7-direct,c86-4g-m7-fpu0")

(define_insn_reservation "c86_4g_m7_mmx_mul_load" 10
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "mmxmul")
				   (eq_attr "memory" "load")))
			  "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu0")

;; PINSR
(define_insn_reservation "c86_4g_m7_sse_pinsr_reg" 1
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sselog,mmxcvt")
				   (and (eq_attr "c86_attr" "insr")
				    (and (eq_attr "prefix" "orig")
					 (eq_attr "memory" "none")))))
			 "c86-4g-m7-direct,c86-4g-m7-fpu")

(define_insn_reservation "c86_4g_m7_sse_pinsr_reg_load" 3
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sselog,mmxcvt")
				   (and (eq_attr "c86_attr" "insr")
				    (and (eq_attr "prefix" "orig")
					 (eq_attr "memory" "load")))))
			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu")

(define_insn_reservation "c86_4g_m7_avx_vpinsr_reg" 2
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sselog")
				   (and (eq_attr "c86_attr" "insr")
				     (and (eq_attr "prefix" "!orig")
					  (eq_attr "memory" "none")))))
			 "c86-4g-m7-double,c86-4g-m7-fpu_1_3x2")

(define_insn_reservation "c86_4g_m7_avx_vpinsr_reg_load" 8
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sselog")
				   (and (eq_attr "c86_attr" "insr")
				     (and (eq_attr "prefix" "!orig")
					  (eq_attr "memory" "load")))))
			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_1_3")

;; PERM
(define_insn_reservation "c86_4g_m7_avx512_perm_xmm" 3
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sselog")
				   (and (ior (and (eq_attr "c86_attr" "perm2")
						  (eq_attr "mode" "V4SF,V2DF,TI"))
					     (and (eq_attr "c86_attr" "perm")
						  (eq_attr "mode" "V8SF,V4DF,TI,OI")))
					(eq_attr "memory" "none"))))
			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_2x2")

(define_insn_reservation "c86_4g_m7_avx512_perm_xmm_opload" 10
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sselog")
				   (and (ior (and (eq_attr "c86_attr" "perm2")
						  (eq_attr "mode" "V4SF,V2DF,TI"))
					     (and (eq_attr "c86_attr" "perm")
						  (eq_attr "mode" "V8SF,V4DF,TI,OI")))
					(eq_attr "memory" "load"))))
			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2x2")

(define_insn_reservation "c86_4g_m7_avx512_permi2_ymm" 4
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sselog")
				   (and (eq_attr "c86_attr" "perm2")
				    (and (eq_attr "mode" "V8SF,V4DF,OI")
					  (eq_attr "memory" "none")))))
			 "c86-4g-m7-vector,c86-4g-m7-fpux4")

(define_insn_reservation "c86_4g_m7_avx512_permi2_zmm" 16
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sselog")
				   (and (eq_attr "c86_attr" "perm2")
				    (and (eq_attr "mode" "V16SF,V8DF,XI")
					 (eq_attr "memory" "none")))))
			 "c86-4g-m7-vector,c86-4g-m7-fpux16")

(define_insn_reservation "c86_4g_m7_avx512_permi2_ymm_load" 11
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sselog")
				   (and (eq_attr "c86_attr" "perm2")
				    (and (eq_attr "mode" "V8SF,V4DF,OI")
					 (eq_attr "memory" "load")))))
			 "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-fpux4")

(define_insn_reservation "c86_4g_m7_avx512_permi2_zmm_load" 23
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sselog")
				   (and (eq_attr "c86_attr" "perm2")
				    (and (eq_attr "mode" "V16SF,V8DF,XI")
					 (eq_attr "memory" "load")))))
			 "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-fpux16")

(define_insn_reservation "c86_4g_m7_avx512_perm_zmm_imm" 4
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sselog")
				   (and (eq_attr "c86_attr" "perm")
				    (and (eq_attr "mode" "V16SF,V8DF,XI")
				     (and (match_operand 2 "immediate_operand")
					  (eq_attr "memory" "none"))))))
			 "c86-4g-m7-direct,c86-4g-m7-fpux4")

(define_insn_reservation "c86_4g_m7_avx512_perm_zmm_imm_load" 11
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sselog")
				   (and (eq_attr "c86_attr" "perm")
				    (and (eq_attr "mode" "V16SF,V8DF,XI")
				     (and (match_operand 2 "immediate_operand")
					  (eq_attr "memory" "load"))))))
			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpux4")

(define_insn_reservation "c86_4g_m7_avx512_perm_zmm_noimm" 8
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sselog")
				   (and (eq_attr "c86_attr" "perm")
				    (and (eq_attr "mode" "V16SF,V8DF,XI")
				     (and (match_operand 2 "nonimmediate_operand")
					  (eq_attr "memory" "none"))))))
			 "c86-4g-m7-vector,c86-4g-m7-fpux8")

(define_insn_reservation "c86_4g_m7_sse_perm_zmm_noimm_load" 15
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sselog")
				   (and (eq_attr "c86_attr" "perm")
				    (and (eq_attr "mode" "V16SF,V8DF,XI")
				     (and (match_operand 2 "nonimmediate_operand")
					 (eq_attr "memory" "load"))))))
			 "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-fpux8")

;; VINSERT
(define_insn_reservation "c86_4g_m7_avx512_insertx_ymm" 3
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sselog,sselog1")
				   (and (eq_attr "c86_attr" "insertx")
				    (and (eq_attr "mode" "V8SF,V4DF,OI")
				     (and (eq_attr "prefix" "evex")
					  (eq_attr "memory" "none"))))))
			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_2,c86-4g-m7-fpu_0_2")

(define_insn_reservation "c86_4g_m7_avx512_insertx_ymem" 10
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sselog,sselog1")
				   (and (eq_attr "c86_attr" "insertx")
				    (and (eq_attr "mode" "V8SF,V4DF,OI")
				     (and (eq_attr "prefix" "evex")
					  (eq_attr "memory" "load,both"))))))
			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-store,c86-4g-m7-fpu_0_2,c86-4g-m7-fpu_0_2")

(define_insn_reservation "c86_4g_m7_avx512_insertx_zxmm" 5
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sselog")
				   (and (eq_attr "c86_attr" "insertx")
				    (and (eq_attr "mode" "V16SF,V8DF,XI")
				    (and (match_test "GET_MODE_SIZE (GET_MODE (operands[2]))==16")
					 (match_operand 2 "register_operand"))))))
			 "c86-4g-m7-double,c86-4g-m7-fpu_0_2x2,c86-4g-m7-fpu_0_2x2")

(define_insn_reservation "c86_4g_m7_avx512_insertx_zxmem" 12
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sselog")
				   (and (eq_attr "c86_attr" "insertx")
				    (and (eq_attr "mode" "V16SF,V8DF,XI")
				    (and (match_test "GET_MODE_SIZE (GET_MODE (operands[2]))==16")
					  (match_operand 2 "memory_operand"))))))
			 "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu_0_2x2,c86-4g-m7-fpu_0_2x2")

(define_insn_reservation "c86_4g_m7_avx512_insertx_zymm" 1
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sselog")
				   (and (eq_attr "c86_attr" "insertx")
				    (and (eq_attr "mode" "V16SF,V8DF,XI")
				    (and (match_test "GET_MODE_SIZE (GET_MODE (operands[2]))==32")
					  (match_operand 2 "register_operand"))))))
			 "c86-4g-m7-double,c86-4g-m7-fpu_1_3,c86-4g-m7-fpu_1_3")

(define_insn_reservation "c86_4g_m7_avx512_insertx_zymem" 8
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sselog")
				   (and (eq_attr "c86_attr" "insertx")
				    (and (eq_attr "mode" "V16SF,V8DF,XI")
				    (and (match_test "GET_MODE_SIZE (GET_MODE (operands[2]))==32")
					  (match_operand 2 "memory_operand"))))))
			 "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu_1_3")

(define_insn_reservation "c86_4g_m7_avx_insertx_ymm" 3
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sselog,sselog1")
				   (and (eq_attr "c86_attr" "insertx")
				     (and (eq_attr "prefix" "!evex")
					  (eq_attr "memory" "none")))))
			 "c86-4g-m7-direct,c86-4g-m7-fpu0*2")

(define_insn_reservation "c86_4g_m7_avx_insertx_ymem" 10
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sselog,sselog1")
				   (and (eq_attr "c86_attr" "insertx")
				     (and (eq_attr "prefix" "!evex")
					  (eq_attr "memory" "load")))))
			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu0*2")

;; SHUF/MULTISHIFTQB
(define_insn_reservation "c86_4g_m7_avx512_shuf_xymm" 3
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sselog")
				   (and (eq_attr "c86_attr" "shufx")
				     (and (not (eq_attr "mode" "V8DF,V16SF,XI"))
					  (eq_attr "memory" "none")))))
			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_2x2")

(define_insn_reservation "c86_4g_m7_avx512_shuf_zmm" 4
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sselog")
				   (and (eq_attr "c86_attr" "shufx")
				     (and (eq_attr "mode" "V8DF,V16SF,XI")
					  (eq_attr "memory" "none")))))
			 "c86-4g-m7-vector,c86-4g-m7-fpu_0_2x4")

(define_insn_reservation "c86_4g_m7_avx512_shuf_xymem" 10
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sselog")
				   (and (eq_attr "c86_attr" "shufx")
				     (and (not (eq_attr "mode" "V8DF,V16SF,XI"))
					  (eq_attr "memory" "load")))))
			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2x2")

(define_insn_reservation "c86_4g_m7_avx512_shuf_zmem" 11
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sselog")
				   (and (eq_attr "c86_attr" "shufx")
				     (and (eq_attr "mode" "V8DF,V16SF,XI")
					  (eq_attr "memory" "load")))))
			 "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-fpu_0_2x4")

;; SSELOGIC
(define_insn_reservation "c86_4g_m7_sselogic_xymm" 1
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sselog,sselog1")
				   (and (eq_attr "c86_attr" "sselogic")
					 (eq_attr "memory" "none"))))
			 "c86-4g-m7-direct,c86-4g-m7-fpu")

(define_insn_reservation "c86_4g_m7_sselogic_xymm_load" 8
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sselog,sselog1")
				   (and (eq_attr "c86_attr" "sselogic")
					 (eq_attr "memory" "load"))))
			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu")

;; CMPESTR
(define_insn_reservation "c86_4g_m7_avx512_cmpestr" 6
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sselog")
				   (and (eq_attr "c86_attr" "cmpestr")
					(eq_attr "memory" "none"))))
			 "c86-4g-m7-vector,c86-4g-m7-fpux6")

(define_insn_reservation "c86_4g_m7_avx512_cmpestr_load" 13
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sselog")
				   (and (eq_attr "c86_attr" "cmpestr")
					(eq_attr "memory" "load"))))
			 "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-fpux6")

;; SSELOG
(define_insn_reservation "c86_4g_m7_avx512_log" 1
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sselog,sselog1,sseshuf,sseshuf1")
				   (and (eq_attr "c86_attr" "other")
					  (eq_attr "memory" "none"))))
			 "c86-4g-m7-direct,c86-4g-m7-fpu_1_3")

(define_insn_reservation "c86_4g_m7_avx512_log_load" 8
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sselog,sselog1,sseshuf,sseshuf1")
				   (and (eq_attr "c86_attr" "other")
					 (eq_attr "memory" "load"))))
			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_1_3")

;; SSELOG1
;; VDBPSADBW
(define_insn_reservation "c86_4g_m7_avx512_vdbpsadbw_xymm" 4
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sselog1")
				   (and (eq_attr "c86_attr" "sadbw")
				    (and (eq_attr "mode" "OI,TI")
					 (eq_attr "memory" "none")))))
			 "c86-4g-m7-double,c86-4g-m7-fpu_0_2,c86-4g-m7-fpu_1_3")

(define_insn_reservation "c86_4g_m7_avx512_vdbpsadbw_xymem" 11
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sselog1")
				   (and (eq_attr "c86_attr" "sadbw")
				    (and (eq_attr "mode" "OI,TI")
					 (eq_attr "memory" "load")))))
			 "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu_0_2,c86-4g-m7-fpu_1_3")

(define_insn_reservation "c86_4g_m7_avx512_vdbpsadbw_zmm" 4
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sselog1")
				   (and (eq_attr "c86_attr" "sadbw")
				    (and (eq_attr "mode" "XI")
					 (eq_attr "memory" "none")))))
			 "c86-4g-m7-vector,c86-4g-m7-fpu_0_2,c86-4g-m7-fpu_1_3x2")

(define_insn_reservation "c86_4g_m7_avx512_vdbpsadbw_zmem" 11
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sselog1")
				   (and (eq_attr "c86_attr" "sadbw")
				    (and (eq_attr "mode" "XI")
					 (eq_attr "memory" "load")))))
			 "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-fpu_0_2,c86-4g-m7-fpu_1_3x2")

;; ABS
(define_insn_reservation "c86_4g_m7_avx512_abs" 1
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sselog1,sse")
				   (and (eq_attr "c86_attr" "abs")
				    (and (eq_attr "prefix" "evex")
					 (eq_attr "memory" "none")))))
			 "c86-4g-m7-direct,c86-4g-m7-fpu")

(define_insn_reservation "c86_4g_m7_avx512_abs_load" 8
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sselog1,sse")
				   (and (eq_attr "c86_attr" "abs")
				    (and (eq_attr "prefix" "evex")
					 (eq_attr "memory" "load,both")))))
			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-store,c86-4g-m7-fpu")

;; SIGN
(define_insn_reservation "c86_4g_m7_avx_sign" 1
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sselog1")
				   (and (eq_attr "c86_attr" "sign")
					(eq_attr "memory" "none"))))
			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_3")

(define_insn_reservation "c86_4g_m7_avx_sign_load" 8
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sselog1")
				   (and (eq_attr "c86_attr" "sign")
					(eq_attr "memory" "!none"))))
			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_3")

;; BLEND/ABS/AES
(define_insn_reservation "c86_4g_m7_avx_blend" 1
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sselog1")
				   (and (eq_attr "c86_attr" "abs,blend,aes")
				    (and (eq_attr "prefix" "!evex")
					 (eq_attr "memory" "none")))))
			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_1")

(define_insn_reservation "c86_4g_m7_avx_blend_load" 8
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sselog1")
				   (and (eq_attr "c86_attr" "abs,blend,aes")
				    (and (eq_attr "prefix" "!evex")
					 (eq_attr "memory" "load")))))
			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_1")

(define_insn_reservation "c86_4g_m7_avx512_aes" 3
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sselog1,ssecvt,sse")
				   (and (eq_attr "c86_attr" "aes")
				    (and (eq_attr "prefix" "evex")
					 (eq_attr "memory" "none")))))
			 "c86-4g-m7-direct,c86-4g-m7-fpu_1_3")

(define_insn_reservation "c86_4g_m7_avx512_aes_load" 10
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sselog1,ssecvt,sse")
				   (and (eq_attr "c86_attr" "aes")
				    (and (eq_attr "prefix" "evex")
					 (eq_attr "memory" "load")))))
			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_1_3")

(define_insn_reservation "c86_4g_m7_avx_aes" 3
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sselog1")
				   (and (eq_attr "c86_attr" "aes")
				    (and (eq_attr "prefix" "!evex")
					 (eq_attr "memory" "none")))))
			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_1")

(define_insn_reservation "c86_4g_m7_avx_aes_load" 10
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sselog1")
				   (and (eq_attr "c86_attr" "aes")
				    (and (eq_attr "prefix" "!evex")
					 (eq_attr "memory" "load")))))
			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_1")

;; EXTR
(define_insn_reservation "c86_4g_m7_extr" 5
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sselog1,sselog,mmxcvt")
				   (and (eq_attr "c86_attr" "extr")
					(eq_attr "memory" "none"))))
			 "c86-4g-m7-double,c86-4g-m7-fpu1,c86-4g-m7-fpu_0_1")

(define_insn_reservation "c86_4g_m7_extr_store" 12
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sselog1,sselog,mmxcvt")
				   (and (eq_attr "c86_attr" "extr")
					(eq_attr "memory" "store"))))
			 "c86-4g-m7-double,c86-4g-m7-store,c86-4g-m7-fpu1,c86-4g-m7-fpu_0_1")

;; SSECOMI
(define_insn_reservation "c86_4g_m7_avx_ssecomi_comi" 1
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "ssecomi")
				   (and (eq_attr "prefix_extra" "0")
					(eq_attr "memory" "none"))))
			 "c86-4g-m7-double,c86-4g-m7-fpu")

(define_insn_reservation "c86_4g_m7_avx_ssecomi_comi_load" 8
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "ssecomi")
				   (and (eq_attr "prefix_extra" "0")
					(eq_attr "memory" "load"))))
			 "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu")

(define_insn_reservation "c86_4g_m7_avx_ssecomi_test" 1
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "ssecomi")
				   (and (eq_attr "prefix_extra" "1")
					(eq_attr "memory" "none"))))
			 "c86-4g-m7-direct,c86-4g-m7-fpu1|c86-4g-m7-fpu2")

(define_insn_reservation "c86_4g_m7_avx_ssecomi_test_load" 8
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "ssecomi")
				   (and (eq_attr "prefix_extra" "1")
					(eq_attr "memory" "load"))))
			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu1|c86-4g-m7-fpu2")

;; SSEIMUL
(define_insn_reservation "c86_4g_m7_avx512_imul" 3
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sseimul")
				   (and (eq_attr "prefix" "evex")
					(eq_attr "memory" "none"))))
			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_2")

(define_insn_reservation "c86_4g_m7_avx512_imul_mem" 10
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sseimul")
				   (and (eq_attr "prefix" "evex")
					(eq_attr "memory" "load"))))
			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2")

(define_insn_reservation "c86_4g_m7_avx_imul" 3
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sseimul")
				   (and (eq_attr "prefix" "!evex")
					(eq_attr "memory" "none"))))
			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_3")

(define_insn_reservation "c86_4g_m7_avx_imul_mem" 10
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sseimul")
				   (and (eq_attr "prefix" "!evex")
					(eq_attr "memory" "load"))))
			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_3")

;; SSEMOV
(define_insn_reservation "c86_4g_m7_avx512_mov_vmov" 1
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "ssemov,sseiadd")
				    (and (eq_attr "c86_attr" "other,blend,maxmin")
					 (eq_attr "memory" "none"))))
			 "c86-4g-m7-direct,c86-4g-m7-fpu")

(define_insn_reservation "c86_4g_m7_avx512_mov_vmov_store" 8
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "ssemov")
				   (and (eq_attr "c86_attr" "other")
					(eq_attr "memory" "store"))))
			 "c86-4g-m7-direct,c86-4g-m7-store,c86-4g-m7-fpu1")

(define_insn_reservation "c86_4g_m7_avx512_mov_vmov_load" 8
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "ssemov,sseiadd")
				   (and (eq_attr "c86_attr" "other,blend,maxmin")
					(eq_attr "memory" "load"))))
			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu")

(define_insn_reservation "c86_4g_m7_avx512_vpmovx_y" 3
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "ssemov")
				   (and (eq_attr "c86_attr" "vpmovx")
				    (and (eq_attr "prefix" "evex")
				     (and (eq_attr "mode" "OI,V8SF,V4DF")
					  (eq_attr "memory" "none"))))))
			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_2x2")

(define_insn_reservation "c86_4g_m7_avx512_vpmovx_y_load" 10
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "ssemov,sselog1")
				   (and (eq_attr "c86_attr" "vpmovx")
				    (and (eq_attr "prefix" "evex")
				     (and (eq_attr "mode" "OI,V8SF,V4DF")
					  (eq_attr "memory" "load,both"))))))
			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-store,c86-4g-m7-fpu_0_2x2")

(define_insn_reservation "c86_4g_m7_avx512_vpmovx_z" 5
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "ssemov")
				   (and (eq_attr "c86_attr" "vpmovx")
				     (and (eq_attr "mode" "XI")
					  (eq_attr "memory" "none")))))
			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_2x4")

(define_insn_reservation "c86_4g_m7_avx512_vpmovx_z_load" 12
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "ssemov")
				   (and (eq_attr "c86_attr" "vpmovx")
				     (and (eq_attr "mode" "XI")
					  (eq_attr "memory" "load")))))
			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2x4")

(define_insn_reservation "c86_4g_m7_avx512_vpmovx_x" 1
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "ssemov")
				   (and (eq_attr "c86_attr" "vpmovx")
				    (and (eq_attr "prefix" "evex")
				     (and (eq_attr "mode" "TI,SI")
					  (eq_attr "memory" "none"))))))
			 "c86-4g-m7-direct,c86-4g-m7-fpu_1_3")

(define_insn_reservation "c86_4g_m7_avx512_vpmovx_x_load" 8
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "ssemov")
				   (and (eq_attr "c86_attr" "vpmovx")
				    (and (eq_attr "prefix" "evex")
				     (and (eq_attr "mode" "TI,SI")
					  (eq_attr "memory" "load"))))))
			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_1_3")

(define_insn_reservation "c86_4g_m7_avx_vpmovx_xx" 1
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "ssemov")
				   (and (eq_attr "c86_attr" "vpmovx")
				    (and (eq_attr "prefix" "!evex")
					 (eq_attr "memory" "none")))))
			 "c86-4g-m7-direct,c86-4g-m7-fpu1|c86-4g-m7-fpu2")

(define_insn_reservation "c86_4g_m7_avx_vpmovx_xx_load" 8
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "ssemov")
				   (and (eq_attr "c86_attr" "vpmovx")
				    (and (eq_attr "prefix" "!evex")
					 (eq_attr "memory" "load,both")))))
			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-store,c86-4g-m7-fpu1|c86-4g-m7-fpu2")

;; EXPAND
(define_insn_reservation "c86_4g_m7_avx512_expand" 3
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "ssemov")
				   (and (eq_attr "c86_attr" "expand,compress")
				    (and (not (eq_attr "mode" "XI,V16SF,V8DF"))
					 (eq_attr "memory" "none")))))
			 "c86-4g-m7-direct,c86-4g-m7-fpu3,c86-4g-m7-fpu_0_3")

(define_insn_reservation "c86_4g_m7_avx512_expand_load" 10
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "ssemov")
				   (and (eq_attr "c86_attr" "expand,compress")
				    (and (not (eq_attr "mode" "XI,V16SF,V8DF"))
					 (eq_attr "memory" "load")))))
			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu3,c86-4g-m7-fpu_0_3")

(define_insn_reservation "c86_4g_m7_avx512_expand_z" 10
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "ssemov")
				   (and (eq_attr "c86_attr" "expand,compress")
				    (and (eq_attr "mode" "XI,V16SF,V8DF")
					 (eq_attr "memory" "none")))))
			 "c86-4g-m7-vector,c86-4g-m7-fpu3,c86-4g-m7-fpu_0_3")

(define_insn_reservation "c86_4g_m7_avx512_expand_z_load" 17
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "ssemov")
				   (and (eq_attr "c86_attr" "expand,compress")
				    (and (eq_attr "mode" "XI,V16SF,V8DF")
					 (eq_attr "memory" "load")))))
			 "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-fpu3,c86-4g-m7-fpu_0_3")

;; MOVNT
(define_insn_reservation "c86_4g_m7_avx512_movnt_load" 8
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "ssemov")
				   (and (eq_attr "c86_attr" "movnt")
				   (and (eq_attr "mode" "XI,V16SF,V8DF")
					(eq_attr "memory" "load")))))
			 "c86-4g-m7-double,c86-4g-m7-load")

(define_insn_reservation "c86_4g_m7_avx512_movnt_store" 8
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "ssemov")
				   (and (eq_attr "c86_attr" "movnt")
				    (and (eq_attr "mode" "XI,V16SF,V8DF")
					 (eq_attr "memory" "store")))))
			 "c86-4g-m7-direct,c86-4g-m7-store,c86-4g-m7-fpu1*2")

(define_insn_reservation "c86_4g_m7_sse_movnt_store" 4
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "ssemov,mmxmov")
				   (and (eq_attr "c86_attr" "movnt")
				    (and (not (eq_attr "mode" "XI,V16SF,V8DF"))
					 (eq_attr "memory" "!none")))))
			 "c86-4g-m7-direct,c86-4g-m7-store,c86-4g-m7-fpu1")

(define_insn_reservation "c86_4g_m7_sse_movnt" 4
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "ssemov")
				   (and (eq_attr "c86_attr" "movnt")
				    (and (not (eq_attr "mode" "XI,V16SF,V8DF"))
					 (eq_attr "memory" "none")))))
			 "c86-4g-m7-direct,c86-4g-m7-fpu_1_3")

;; BLENDV
(define_insn_reservation "c86_4g_m7_avx512_blendv" 1
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "ssemov")
				   (and (eq_attr "c86_attr" "blendv")
					(eq_attr "memory" "none"))))
			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_1")

(define_insn_reservation "c86_4g_m7_avx512_blendv_load" 8
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "ssemov")
				   (and (eq_attr "c86_attr" "blendv")
					(eq_attr "memory" "load"))))
			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_1")

;; SSEMOV2
(define_insn_reservation "c86_4g_m7_sse_mov2" 1
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "ssemov2")
				   (eq_attr "memory" "none")))
			 "c86-4g-m7-direct,c86-4g-m7-fpu")

(define_insn_reservation "c86_4g_m7_sse_mov2_load" 8
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "ssemov2")
				   (eq_attr "memory" "!none")))
			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu")

;; SSEISHFT
(define_insn_reservation "c86_4g_m7_avx512_sseishft_aligr" 1
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sseishft")
				   (and (eq_attr "prefix_extra" "1")
				    (and (eq_attr "prefix" "evex")
					 (eq_attr "memory" "none")))))
			 "c86-4g-m7-direct,c86-4g-m7-fpu_1_3")

(define_insn_reservation "c86_4g_m7_avx512_sseishft_aligr_load" 8
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sseishft")
				   (and (eq_attr "prefix_extra" "1")
				    (and (eq_attr "prefix" "evex")
					 (eq_attr "memory" "load")))))
			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_1_3")

(define_insn_reservation "c86_4g_m7_avx512_sseishft_vshift" 1
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sseishft")
				   (and (eq_attr "prefix_extra" "!1")
					(eq_attr "memory" "none"))))
			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_2")

(define_insn_reservation "c86_4g_m7_avx512_sseishft_vshift_load" 8
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sseishft")
				   (and (eq_attr "prefix_extra" "!1")
					(eq_attr "memory" "!none"))))
			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2")


;; SSEADD
(define_insn_reservation "c86_4g_m7_avx512_sseadd_maxmin" 1
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sseadd,sse")
				   (and (eq_attr "c86_attr" "maxmin")
				    (and (eq_attr "prefix" "evex")
				         (eq_attr "memory" "none")))))
			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_2")

(define_insn_reservation "c86_4g_m7_avx512_sseadd_maxmin_load" 8
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sseadd,sse")
				   (and (eq_attr "c86_attr" "maxmin")
				    (and (eq_attr "prefix" "evex")
					 (eq_attr "memory" "load")))))
			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2")

(define_insn_reservation "c86_4g_m7_avx_sseadd_maxmin" 1
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sseadd,sse")
				   (and (eq_attr "c86_attr" "maxmin")
				    (and (eq_attr "prefix" "vex")
					 (eq_attr "memory" "none")))))
			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_1")

(define_insn_reservation "c86_4g_m7_avx_sseadd_maxmin_load" 8
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sseadd,sse")
				   (and (eq_attr "c86_attr" "maxmin")
				    (and (eq_attr "prefix" "vex")
					 (eq_attr "memory" "load")))))
			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_1")

(define_insn_reservation "c86_4g_m7_sse_sseadd_maxmin" 1
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sseadd,sse")
				   (and (eq_attr "c86_attr" "maxmin")
				    (and (eq_attr "prefix" "orig")
					 (eq_attr "memory" "none")))))
			 "c86-4g-m7-direct,c86-4g-m7-fpu2|c86-4g-m7-fpu3")

(define_insn_reservation "c86_4g_m7_sse_sseadd_maxmin_load" 8
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sseadd,sse")
				   (and (eq_attr "c86_attr" "maxmin")
				    (and (eq_attr "prefix" "orig")
					 (eq_attr "memory" "load")))))
			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu2|c86-4g-m7-fpu3")

;; SUB/ADD
(define_insn_reservation "c86_4g_m7_avx512_sseadd" 3
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sseadd")
				   (and (eq_attr "c86_attr" "other")
					(eq_attr "memory" "none"))))
			 "c86-4g-m7-direct,c86-4g-m7-fpu_1_3")

(define_insn_reservation "c86_4g_m7_avx512_sseadd_load" 10
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sseadd")
				   (and (eq_attr "c86_attr" "other")
					(eq_attr "memory" "load"))))
			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_1_3")

;; HADD/HSUB
(define_insn_reservation "c86_4g_m7_avx_sseadd_hplus" 7
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sseadd,sseadd1")
				   (and (eq_attr "c86_attr" "hplus")
					(eq_attr "memory" "none"))))
			 "c86-4g-m7-vector")

(define_insn_reservation "c86_4g_m7_avx_sseadd_hplus_load" 14
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sseadd,sseadd1")
				   (and (eq_attr "c86_attr" "hplus")
					(eq_attr "memory" "load"))))
			 "c86-4g-m7-vector,c86-4g-m7-load")

;; SSEIADD
(define_insn_reservation "c86_4g_m7_avx512_sseiadd_madd" 3
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sseiadd")
				   (and (eq_attr "c86_attr" "sadbw,madd")
					(and (ior (eq_attr "prefix" "evex")
						  (eq_attr "mode" "XI"))
					     (eq_attr "memory" "none")))))
			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_2")

(define_insn_reservation "c86_4g_m7_avx512_sseiadd_madd_mem" 10
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sseiadd")
				   (and (eq_attr "c86_attr" "sadbw,madd")
					(and (ior (eq_attr "prefix" "evex")
						  (eq_attr "mode" "XI"))
					     (eq_attr "memory" "load")))))
			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2")

(define_insn_reservation "c86_4g_m7_avx_sseiadd_sadbw" 3
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sseiadd")
				   (and (eq_attr "c86_attr" "sadbw")
				    (and (eq_attr "prefix" "vex,maybe_evex")
				     (and (eq_attr "mode" "TI,OI")
					  (eq_attr "memory" "none"))))))
			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_1")

(define_insn_reservation "c86_4g_m7_avx_sseiadd_sadbw_mem" 10
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sseiadd")
				   (and (eq_attr "c86_attr" "sadbw")
				    (and (eq_attr "prefix" "vex,maybe_evex")
				     (and (eq_attr "mode" "TI,OI")
					  (eq_attr "memory" "load"))))))
			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_1")

(define_insn_reservation "c86_4g_m7_sse_sseiadd_sadbw" 3
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sseiadd")
				   (and (eq_attr "c86_attr" "sadbw")
				    (and (eq_attr "prefix" "orig")
					 (eq_attr "memory" "none")))))
			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_3")

(define_insn_reservation "c86_4g_m7_sse_sseiadd_sadbw_mem" 10
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sseiadd")
				   (and (eq_attr "c86_attr" "sadbw")
				    (and (eq_attr "prefix" "orig")
					 (eq_attr "memory" "load")))))
			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_3")

(define_insn_reservation "c86_4g_m7_sse_sseiadd_madd" 3
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sseiadd")
				   (and (eq_attr "c86_attr" "madd")
				    (and (eq_attr "prefix" "!evex")
					 (eq_attr "memory" "none")))))
			 "c86-4g-m7-direct,c86-4g-m7-fpu0")

(define_insn_reservation "c86_4g_m7_sse_sseiadd_madd_mem" 10
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sseiadd")
				   (and (eq_attr "c86_attr" "madd")
				    (and (eq_attr "prefix" "!evex")
					 (eq_attr "memory" "load")))))
			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu0")

;; AVG
(define_insn_reservation "c86_4g_m7_avx512_sseiadd_avg" 1
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sseiadd")
				   (and (eq_attr "c86_attr" "avg")
					(eq_attr "memory" "none"))))
			 "c86-4g-m7-direct,c86-4g-m7-fpu")

(define_insn_reservation "c86_4g_m7_avx512_sseiadd_avg_load" 8
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sseiadd")
				   (and (eq_attr "c86_attr" "avg")
					(eq_attr "memory" "load"))))
			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu")

(define_insn_reservation "c86_4g_m7_avx_sseiadd_hplus" 3
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sseiadd,sseiadd1")
				   (and (eq_attr "c86_attr" "hplus")
				    (and (eq_attr "prefix" "vex")
					 (eq_attr "memory" "none")))))
			 "c86-4g-m7-vector")

(define_insn_reservation "c86_4g_m7_avx_sseiadd_hplus_load" 10
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sseiadd,sseiadd1")
				   (and (eq_attr "c86_attr" "hplus")
				    (and (eq_attr "prefix" "vex")
					 (eq_attr "memory" "load")))))
			 "c86-4g-m7-vector,c86-4g-m7-load")

(define_insn_reservation "c86_4g_m7_sse_sseiadd_hplus" 3
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sseiadd,sseiadd1")
				   (and (eq_attr "c86_attr" "hplus")
				    (and (eq_attr "prefix" "orig")
					 (eq_attr "memory" "none")))))
			 "c86-4g-m7-vector,c86-4g-m7-fpux2")

(define_insn_reservation "c86_4g_m7_sse_sseiadd_hplus_load" 10
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sseiadd,sseiadd1")
				   (and (eq_attr "c86_attr" "hplus")
				    (and (eq_attr "prefix" "orig")
					 (eq_attr "memory" "load")))))
			 "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-fpux2")

;; SSEMUL
(define_insn_reservation "c86_4g_m7_avx512_ssemul" 3
			 (and (eq_attr "cpu" "c86_4g_m7")
			      (and (eq_attr "type" "ssemul")
				   (eq_attr "memory" "none")))
			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_2")

(define_insn_reservation "c86_4g_m7_avx512_ssemul_load" 10
			 (and (eq_attr "cpu" "c86_4g_m7")
			      (and (eq_attr "type" "ssemul")
				   (eq_attr "memory" "load")))
			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2")

(define_insn_reservation "c86_4g_m8_avx512_ssemul" 4
			 (and (eq_attr "cpu" "c86_4g_m8")
			      (and (eq_attr "type" "ssemul")
				   (eq_attr "memory" "none")))
			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_2")

(define_insn_reservation "c86_4g_m8_avx512_ssemul_load" 11
			 (and (eq_attr "cpu" "c86_4g_m8")
			      (and (eq_attr "type" "ssemul")
				   (eq_attr "memory" "load")))
			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2")

;; SSEDIV
(define_insn_reservation "c86_4g_m7_avx512_ssediv_x" 13
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "ssediv")
				   (and (eq_attr "mode" "SF,DF,V4SF,V2DF")
					(eq_attr "memory" "none"))))
			 "c86-4g-m7-direct,c86-4g-m7-fp1div1_fp3div3_x4x8")

(define_insn_reservation "c86_4g_m7_avx512_ssediv_xmem" 20
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "ssediv")
				   (and (eq_attr "mode" "SF,DF,V4SF,V2DF")
					(eq_attr "memory" "load"))))
			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fp1div1_fp3div3_x4x8")

(define_insn_reservation "c86_4g_m7_avx512_ssediv_y" 13
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "ssediv")
				   (and (eq_attr "mode" "V8SF,V4DF")
					(eq_attr "memory" "none"))))
			 "c86-4g-m7-direct,c86-4g-m7-fp13div13x4,c86-4g-m7-fdiv13*8")

(define_insn_reservation "c86_4g_m7_avx512_ssediv_ymem" 20
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "ssediv")
				   (and (eq_attr "mode" "V8SF,V4DF")
					(eq_attr "memory" "load"))))
			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fp13div13x4,c86-4g-m7-fdiv13*8")

(define_insn_reservation "c86_4g_m7_avx512_ssediv_z" 24
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "ssediv")
				   (and (eq_attr "mode" "V16SF,V8DF")
					(eq_attr "memory" "none"))))
			 "c86-4g-m7-double,c86-4g-m7-fp13div13x4,c86-4g-m7-fdiv13*20")

(define_insn_reservation "c86_4g_m7_avx512_ssediv_zmem" 31
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "ssediv")
				   (and (eq_attr "mode" "V16SF,V8DF")
					 (eq_attr "memory" "load"))))
			 "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fp13div13x4,c86-4g-m7-fdiv13*20")

;; SSECMP
(define_insn_reservation "c86_4g_m7_avx512_ssecmp" 5
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "ssecmp")
				   (and (eq_attr "prefix" "evex")
				    (and (eq_attr "mode" "V2DF,V4DF,V8SF,V4SF,SF,DF")
					 (eq_attr "memory" "none")))))
			 "c86-4g-m7-double,c86-4g-m7-fpu_0_2,c86-4g-m7-fpu_1_3")

(define_insn_reservation "c86_4g_m7_avx512_ssecmp_load" 12
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "ssecmp")
				   (and (eq_attr "prefix" "evex")
				    (and (eq_attr "mode" "V2DF,V4DF,V8SF,V4SF,SF,DF")
					 (eq_attr "memory" "load")))))
			 "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu_0_2,c86-4g-m7-fpu_1_3")

(define_insn_reservation "c86_4g_m7_avx512_ssecmp_z" 5
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "ssecmp")
				    (and (eq_attr "mode" "V16SF,V8DF,XI")
				     (and (eq_attr "c86_attr" "other")
					  (eq_attr "memory" "none")))))
			 "c86-4g-m7-vector,c86-4g-m7-fpu_0_2,c86-4g-m7-fpu_1_3")

(define_insn_reservation "c86_4g_m7_avx512_ssecmp_z_load" 12
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "ssecmp")
				    (and (eq_attr "mode" "V16SF,V8DF,XI")
				     (and (eq_attr "c86_attr" "other")
					  (eq_attr "memory" "load")))))
			 "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-fpu_0_2,c86-4g-m7-fpu_1_3x2")

(define_insn_reservation "c86_4g_m7_avx512_ssecmp_vp" 5
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "ssecmp")
				   (and (eq_attr "prefix" "evex")
				    (and (eq_attr "mode" "TI,OI")
				     (and (eq_attr "c86_attr" "other")
					  (eq_attr "memory" "none"))))))
			 "c86-4g-m7-double,c86-4g-m7-fpu,c86-4g-m7-fpu_1_3")

(define_insn_reservation "c86_4g_m7_avx512_ssecmp_vp_load" 12
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "ssecmp")
				   (and (eq_attr "prefix" "evex")
				    (and (eq_attr "mode" "TI,OI")
				     (and (eq_attr "c86_attr" "other")
					  (eq_attr "memory" "load"))))))
			 "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu,c86-4g-m7-fpu_1_3")

(define_insn_reservation "c86_4g_m7_avx512_ssecmp_vp_z" 5
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "ssecmp")
				   (and (eq_attr "prefix" "evex")
				    (and (eq_attr "mode" "XI")
				     (and (eq_attr "c86_attr" "other,ptest")
					  (eq_attr "memory" "none"))))))
			 "c86-4g-m7-vector,c86-4g-m7-fpu,c86-4g-m7-fpu_1_3")

(define_insn_reservation "c86_4g_m7_avx512_ssecmp_vp_z_load" 12
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "ssecmp")
				   (and (eq_attr "prefix" "evex")
				    (and (eq_attr "mode" "XI")
				     (and (eq_attr "c86_attr" "other,ptest")
					  (eq_attr "memory" "load"))))))
			 "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-fpu,c86-4g-m7-fpu_1_3x2")

(define_insn_reservation "c86_4g_m7_avx_ssecmp_vp" 1
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "ssecmp")
				   (and (eq_attr "prefix" "!evex")
					(eq_attr "memory" "none"))))
			 "c86-4g-m7-direct,c86-4g-m7-fpu")

(define_insn_reservation "c86_4g_m7_avx_ssecmp_vp_load" 8
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "ssecmp")
				   (and (eq_attr "prefix" "!evex")
					(eq_attr "memory" "load"))))
			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu")

;; VPTEST
(define_insn_reservation "c86_4g_m7_avx512_ssecmp_test" 6
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "ssecmp")
				    (and (eq_attr "mode" "TI,OI")
				     (and (eq_attr "c86_attr" "ptest")
					  (eq_attr "memory" "none")))))
			 "c86-4g-m7-double,c86-4g-m7-fpu,c86-4g-m7-fpu_1_3")

(define_insn_reservation "c86_4g_m7_avx512_ssecmp_test_load" 13
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "ssecmp")
				    (and (eq_attr "mode" "TI,OI")
				     (and (eq_attr "c86_attr" "ptest")
					  (eq_attr "memory" "load")))))
			 "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu,c86-4g-m7-fpu_1_3")

;; SSECVT
(define_insn_reservation "c86_4g_m7_avx512_ssecvt_xy" 4
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "ssecvt")
				   (and (eq_attr "c86_attr" "other")
				    (and (eq_attr "prefix" "evex")
				     (and (eq_attr "mode" "TI,V4SF,V2DF,OI,V8SF,V4DF")
				      (and (not (ior (match_operand:V8DI 1 "register_operand")
						     (match_operand:V8DF 1 "register_operand")))
					   (eq_attr "memory" "none")))))))
			 "c86-4g-m7-direct,c86-4g-m7-fpu_1_3")

(define_insn_reservation "c86_4g_m7_avx512_ssecvt_xy_load" 11
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "ssecvt")
				   (and (eq_attr "prefix" "evex")
				    (and (eq_attr "c86_attr" "other")
				     (and (eq_attr "mode" "TI,V4SF,V2DF,OI,V8SF,V4DF")
				      (and (not (ior (match_operand:V8DI 1 "register_operand")
						     (match_operand:V8DF 1 "register_operand")))
					   (eq_attr "memory" "!none")))))))
			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_1_3")

(define_insn_reservation "c86_4g_m7_avx512_ssecvt_y_z" 8
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "ssecvt")
				   (and (eq_attr "mode" "OI,V8SF,V4DF")
				    (and (eq_attr "c86_attr" "other")
				     (and (ior (match_operand:V8DI 1 "register_operand")
					       (match_operand:V8DF 1 "register_operand"))
					  (eq_attr "memory" "none"))))))
			 "c86-4g-m7-double,c86-4g-m7-fpu_1_3")

(define_insn_reservation "c86_4g_m7_avx512_ssecvt_y_z_load" 15
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "ssecvt")
				   (and (eq_attr "mode" "OI,V8SF,V4DF")
				    (and (eq_attr "c86_attr" "other")
				     (and (ior (match_operand:V8DI 1 "memory_operand")
					       (match_operand:V8DF 1 "memory_operand"))
					  (eq_attr "memory" "!none"))))))
			 "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu_1_3")

(define_insn_reservation "c86_4g_m7_avx512_ssecvt_z" 4
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "ssecvt")
				   (and (eq_attr "c86_attr" "other")
				    (and (eq_attr "mode" "XI,V16SF,V8DF")
					 (eq_attr "memory" "none")))))
			 "c86-4g-m7-double,c86-4g-m7-fpu_1_3")

(define_insn_reservation "c86_4g_m7_avx512_ssecvt_z_load" 11
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "ssecvt")
				   (and (eq_attr "c86_attr" "other")
				    (and (eq_attr "mode" "XI,V16SF,V8DF")
					 (eq_attr "memory" "!none")))))
			 "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu_1_3")

(define_insn_reservation "c86_4g_m7_avx_ssecvt" 4
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "ssecvt")
				   (and (eq_attr "prefix" "!evex")
				     (and (eq_attr "mmx_isa" "base")
					  (eq_attr "memory" "none")))))
			 "c86-4g-m7-direct,c86-4g-m7-fpu2|c86-4g-m7-fpu3")

(define_insn_reservation "c86_4g_m7_avx_ssecvt_load" 11
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "ssecvt")
				   (and (eq_attr "prefix" "!evex")
				    (and (eq_attr "mmx_isa" "base")
					 (eq_attr "memory" "!none")))))
			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu2|c86-4g-m7-fpu3")

;; CVTPI
(define_insn_reservation "c86_4g_m7_sse_ssecvt_pspi" 4
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "ssecvt")
				   (and (eq_attr "mode" "SF,DI")
					(eq_attr "memory" "none"))))
			 "c86-4g-m7-direct,c86-4g-m7-fpu1")

(define_insn_reservation "c86_4g_m7_sse_ssecvt_pspi_load" 11
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "ssecvt")
				   (and (eq_attr "mode" "SF,DI")
					 (eq_attr "memory" "load"))))
			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu1")

(define_insn_reservation "c86_4g_m7_sse_ssecvt_pi" 5
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "ssecvt")
				    (and (not (eq_attr "mode" "SF,DI"))
				     (and (eq_attr "mmx_isa" "native")
					  (eq_attr "memory" "none")))))
			 "c86-4g-m7-double,c86-4g-m7-fpu1,c86-4g-m7-fpu_0_1")

(define_insn_reservation "c86_4g_m7_sse_ssecvt_pi_load" 12
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "ssecvt")
				   (and (not (eq_attr "mode" "SF,DI"))
				    (and (eq_attr "mmx_isa" "native")
					 (eq_attr "memory" "load")))))
			 "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu1,c86-4g-m7-fpu_0_1")

;; SSEMULADD
(define_insn_reservation "c86_4g_m7_avx512_muladd" 4
			 (and (eq_attr "cpu" "c86_4g_m7")
			      (and (eq_attr "type" "ssemuladd")
				   (and (eq_attr "c86_attr" "other")
					(eq_attr "memory" "none"))))
			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_2")

(define_insn_reservation "c86_4g_m7_avx512_muladd_load" 11
			 (and (eq_attr "cpu" "c86_4g_m7")
			      (and (eq_attr "type" "ssemuladd")
				   (and (eq_attr "c86_attr" "other")
					(eq_attr "memory" "load"))))
			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2")

(define_insn_reservation "c86_4g_m8_avx512_muladd" 5
			 (and (eq_attr "cpu" "c86_4g_m8")
			      (and (eq_attr "type" "ssemuladd")
				   (and (eq_attr "c86_attr" "other")
					(eq_attr "memory" "none"))))
			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_2")

(define_insn_reservation "c86_4g_m8_avx512_muladd_load" 12
			 (and (eq_attr "cpu" "c86_4g_m8")
			      (and (eq_attr "type" "ssemuladd")
				   (and (eq_attr "c86_attr" "other")
					(eq_attr "memory" "load"))))
			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2")

(define_insn_reservation "c86_4g_m7_avx512_muladd_madd" 4
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "ssemuladd,sse")
				   (and (eq_attr "c86_attr" "madd,rcp")
				    (and (eq_attr "prefix" "evex")
					 (eq_attr "memory" "none")))))
			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_2")

(define_insn_reservation "c86_4g_m7_avx512_muladd_madd_load" 11
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "ssemuladd,sse")
				   (and (eq_attr "c86_attr" "madd,rcp")
				    (and (eq_attr "prefix" "evex")
					 (eq_attr "memory" "load")))))
			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2")

;; SSE
(define_insn_reservation "c86_4g_m7_avx512_sse_range" 1
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sse")
				    (and (eq_attr "c86_attr" "other")
				     (and (eq_attr "length_immediate" "!1")
				      (and (eq_attr "prefix" "evex")
				       (and (eq_attr "c86_decode" "direct")
					   (eq_attr "memory" "none")))))))
			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_2")

(define_insn_reservation "c86_4g_m7_avx512_sse_range_load" 8
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sse")
				    (and (eq_attr "c86_attr" "other")
				     (and (eq_attr "length_immediate" "!1")
				      (and (eq_attr "c86_decode" "direct")
				       (and (eq_attr "prefix" "evex")
					    (eq_attr "memory" "load")))))))
			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2")

(define_insn_reservation "c86_4g_m7_avx512_sse_conflict_x" 2
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sse")
				   (and (eq_attr "c86_decode" "vector")
				    (and (eq_attr "mode" "TI")
					 (eq_attr "memory" "none")))))
			 "c86-4g-m7-vector,c86-4g-m7-fpu_1_3x2")

(define_insn_reservation "c86_4g_m7_avx512_sse_conflict_x_load" 9
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sse")
				   (and (eq_attr "c86_decode" "vector")
				    (and (eq_attr "mode" "TI")
					 (eq_attr "memory" "load")))))
			 "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-fpu_1_3x2")

(define_insn_reservation "c86_4g_m7_avx512_sse_conflict_y" 5
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sse")
				   (and (eq_attr "c86_decode" "vector")
				    (and (eq_attr "mode" "OI")
					 (eq_attr "memory" "none")))))
			 "c86-4g-m7-vector,c86-4g-m7-fpu_1_3x3")

(define_insn_reservation "c86_4g_m7_avx512_sse_conflict_y_load" 12
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sse")
				   (and (eq_attr "c86_decode" "vector")
				    (and (eq_attr "mode" "OI")
					 (eq_attr "memory" "load")))))
			 "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-fpu_1_3x3")

(define_insn_reservation "c86_4g_m7_avx512_sse_conflict_z" 8
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sse")
				   (and (eq_attr "c86_decode" "vector")
				    (and (eq_attr "mode" "XI")
					 (eq_attr "memory" "none")))))
			 "c86-4g-m7-vector,c86-4g-m7-fpu_1_3x6")

(define_insn_reservation "c86_4g_m7_avx512_sse_conflict_z_load" 15
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sse")
				   (and (eq_attr "c86_decode" "vector")
				    (and (eq_attr "mode" "XI")
					 (eq_attr "memory" "load")))))
			 "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-fpu_1_3x6")

(define_insn_reservation "c86_4g_m7_avx512_sse_class" 4
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sse")
				   (and (eq_attr "c86_attr" "other")
				    (and (eq_attr "length_immediate" "1")
				     (and (not (eq_attr "mode" "V32HF,V16SF,V8DF"))
					  (eq_attr "memory" "none"))))))
			 "c86-4g-m7-double,c86-4g-m7-fpu_1_3,c86-4g-m7-fpu_1_3")

(define_insn_reservation "c86_4g_m7_avx512_sse_class_load" 11
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sse")
				    (and (eq_attr "c86_attr" "other")
				     (and (eq_attr "length_immediate" "1")
				      (and (not (eq_attr "mode" "V32HF,V16SF,V8DF"))
					   (eq_attr "memory" "load"))))))
			 "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu_1_3,c86-4g-m7-fpu_1_3")

(define_insn_reservation "c86_4g_m7_avx512_sse_class_z" 4
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sse")
				    (and (eq_attr "c86_attr" "other")
				     (and (eq_attr "length_immediate" "1")
				      (and (eq_attr "mode" "V32HF,V16SF,V8DF")
					   (eq_attr "memory" "none"))))))
			 "c86-4g-m7-vector,c86-4g-m7-fpu_1_3,c86-4g-m7-fpu_1_3")

(define_insn_reservation "c86_4g_m7_avx512_sse_class_z_load" 11
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sse")
				    (and (eq_attr "c86_attr" "other")
				     (and (eq_attr "length_immediate" "1")
				      (and (eq_attr "mode" "V32HF,V16SF,V8DF")
					   (eq_attr "memory" "load"))))))
			 "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-fpu_1_3,c86-4g-m7-fpu_1_3")

(define_insn_reservation "c86_4g_m7_avx_sse" 5
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sse")
				   (and (eq_attr "c86_attr" "rcp,other")
				    (and (eq_attr "prefix" "!evex")
					 (eq_attr "memory" "none")))))
			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_1")

(define_insn_reservation "c86_4g_m7_avx_sse_load" 12
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sse")
				   (and (eq_attr "c86_attr" "rcp,other")
				    (and (eq_attr "prefix" "!evex")
					 (eq_attr "memory" "load")))))
			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_1")

;; SSE SQRT
(define_insn_reservation "c86_4g_m7_avx512_sse_sqrt_sf_x" 14
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sse")
				   (and (eq_attr "mode" "SF,V4SF")
				    (and (eq_attr "c86_attr" "sqrt")
					 (eq_attr "memory" "none")))))
			 "c86-4g-m7-direct,c86-4g-m7-fp1div1_fp3div3_x4x9")

(define_insn_reservation "c86_4g_m7_avx512_sse_sqrt_sf_xload" 21
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sse")
				   (and (eq_attr "mode" "SF,V4SF")
				    (and (eq_attr "c86_attr" "sqrt")
					 (eq_attr "memory" "load")))))
			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fp1div1_fp3div3_x4x9")

(define_insn_reservation "c86_4g_m7_avx512_sse_sqrt_sf_y" 14
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sse")
				   (and (eq_attr "mode" "V8SF")
				    (and (eq_attr "c86_attr" "sqrt")
					 (eq_attr "memory" "none")))))
			 "c86-4g-m7-direct,c86-4g-m7-fp13div13x4,c86-4g-m7-fdiv13*9")

(define_insn_reservation "c86_4g_m7_avx512_sse_sqrt_sf_yload" 21
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sse")
				   (and (eq_attr "mode" "V8SF")
				    (and (eq_attr "c86_attr" "sqrt")
					 (eq_attr "memory" "load")))))
			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fp13div13x4,c86-4g-m7-fdiv13*9")

(define_insn_reservation "c86_4g_m7_avx512_sse_sqrt_sf_z" 26
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sse")
				   (and (eq_attr "mode" "V16SF")
				    (and (eq_attr "c86_attr" "sqrt")
					 (eq_attr "memory" "none")))))
			 "c86-4g-m7-direct,c86-4g-m7-fp13div13x4,c86-4g-m7-fdiv13*22")

(define_insn_reservation "c86_4g_m7_avx512_sse_sqrt_sf_zload" 33
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sse")
				   (and (eq_attr "mode" "V16SF")
				    (and (eq_attr "c86_attr" "sqrt")
					 (eq_attr "memory" "load")))))
			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fp13div13x4,c86-4g-m7-fdiv13*22")

(define_insn_reservation "c86_4g_m7_avx512_sse_sqrt_df_x" 20
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sse")
				   (and (eq_attr "mode" "DF,V2DF")
				    (and (eq_attr "c86_attr" "sqrt")
					 (eq_attr "memory" "none")))))
			 "c86-4g-m7-direct,c86-4g-m7-fp1div1_fp3div3_x4x15")

(define_insn_reservation "c86_4g_m7_avx512_sse_sqrt_df_xload" 27
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sse")
				   (and (eq_attr "mode" "DF,V2DF")
				    (and (eq_attr "c86_attr" "sqrt")
					 (eq_attr "memory" "load")))))
			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fp1div1_fp3div3_x4x15")

(define_insn_reservation "c86_4g_m7_avx512_sse_sqrt_df_y" 20
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sse")
				   (and (eq_attr "mode" "V4DF")
				    (and (eq_attr "c86_attr" "sqrt")
					 (eq_attr "memory" "none")))))
			 "c86-4g-m7-direct,c86-4g-m7-fp13div13x4,c86-4g-m7-fdiv13*15")

(define_insn_reservation "c86_4g_m7_avx512_sse_sqrt_df_yload" 27
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sse")
				   (and (eq_attr "mode" "V4DF")
				    (and (eq_attr "c86_attr" "sqrt")
					 (eq_attr "memory" "load")))))
			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fp13div13x4,c86-4g-m7-fdiv13*15")

(define_insn_reservation "c86_4g_m7_avx512_sse_sqrt_df_z" 38
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sse")
				   (and (eq_attr "mode" "V8DF")
				    (and (eq_attr "c86_attr" "sqrt")
					 (eq_attr "memory" "none")))))
			 "c86-4g-m7-direct,c86-4g-m7-fp13div13x4,c86-4g-m7-fdiv13*34")

(define_insn_reservation "c86_4g_m7_avx512_sse_sqrt_df_zload" 45
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "sse")
				   (and (eq_attr "mode" "V8DF")
				    (and (eq_attr "c86_attr" "sqrt")
					 (eq_attr "memory" "load")))))
			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fp13div13x4,c86-4g-m7-fdiv13*34")

;; MSKLOG/MSKMOV
(define_insn_reservation "c86_4g_m7_avx512_msklog" 1
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "msklog")
				   (eq_attr "c86_decode" "direct")))
			 "c86-4g-m7-direct,c86-4g-m7-fpu_1_3")

(define_insn_reservation "c86_4g_m7_avx512_msklog_vector" 4
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "msklog")
				   (eq_attr "c86_decode" "vector")))
			 "c86-4g-m7-vector,c86-4g-m7-fpu_1_3")

(define_insn_reservation "c86_4g_m7_avx512_mskmov_reg_k" 1
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "mskmov")
				  (and (match_operand 0 "register_operand" "r")
				       (eq_attr "memory" "none"))))
			 "c86-4g-m7-double,c86-4g-m7-fpu3,c86-4g-m7-fpu_1_3")

(define_insn_reservation "c86_4g_m7_avx512_mskmov_xy_k" 2
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "mskmov")
				   (ior (match_operand:V2DI 0 "register_operand" "v")
					(match_operand:V4DI 0 "register_operand" "v"))))
			 "c86-4g-m7-double,c86-4g-m7-fpu3,c86-4g-m7-fpu_1_3")

(define_insn_reservation "c86_4g_m7_avx512_mskmov_z_k" 3
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "mskmov")
				   (match_operand:V8DI 0 "register_operand" "v")))
			 "c86-4g-m7-vector,c86-4g-m7-fpu3,c86-4g-m7-fpu_1_3")

(define_insn_reservation "c86_4g_m7_avx512_mskmov_k_k" 1
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "mskmov")
				  (and (match_operand 0 "register_operand" "k")
				       (match_operand 1 "register_operand" "k"))))
			 "c86-4g-m7-direct,c86-4g-m7-fpu_1_3")

(define_insn_reservation "c86_4g_m7_avx512_mskmov_k_reg" 3
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "mskmov")
				  (and (match_operand 0 "register_operand" "k")
				       (match_operand 1 "register_operand" "r"))))
			 "c86-4g-m7-double,c86-4g-m7-fpu1,c86-4g-m7-fpu_1_3")

(define_insn_reservation "c86_4g_m7_avx512_mskmov_k_m" 9
			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
			      (and (eq_attr "type" "mskmov")
				  (and (match_operand 0 "register_operand" "k")
				       (match_operand 1 "memory_operand"))))
			 "c86-4g-m7-direct,c86-4g-m7-load")
