* I'd like to have a means to define that a goal function is not defined
  for all possible input values.  On extra parameter, ALLOWED_ARGUMENTS, to
  DEF_GOAL could take care of that.

  Also I'd like to add a list of immediate values to try for each goal
  function.  For example, 31 and 32 could be useful for ffs.

* Make it possible to handle more immediate values.

* Interpret goal functions so the user doesn't need to recompile.
  Interpretation would make goal function evaluation slower than it is now,
  but goal function evaluation is not critical.

* Add code to algebraically prove that a generated sequences are correct.

* Add bsrl/bsfl and bfffo to CISC synth.

* Check that PERFORM_CLZ works like RS/6000's cntlz and 29k's clz.  Is it
  ok for input == 0?

* A major speed improvement would be to make independent insn have a
  canonical order.  Consider `gts' on the SPARC.  This is probably not very
  hard, if insns are enumerated in some clever way and loop variables are
  passed down.

  After an instruction that sets carry (and there is another instruction
  with the same effect apart from that it doesn't affect carry), the
  generated carry has to be used.  [Fix this with a reservation vector
  --allow both making and deleting a reservation.  Make reservation when
  carry is generated and delete it when it is used.]  The leaf instructions
  have to munch carry if an unused carry is pending.

  Make sure all computed values are used by subsequent instructions.  For
  example, if we have just two more values to compute and three yet unused
  values, the last two instructions have to restrict their input operands.

* Efficient pruning of sequences not using generated resources:

  Each generated instruction should record it's computed 'resources' in a
  data base of unused resources.  (A written register is such a resource,
  and the carry flag is such a resource.)  When a resource is used by an
  instruction, it's removed from the data base.

  At each recursion, we check that the unused resources can be consumed
  with the allowed number of instructions.  If not, we back-track.

  Beware: A resource is not 'consumed' when it has been used.  I have
  seen optimal sequences that uses a generated carry more than once.

* Shift 32 steps on 68k is well-defined.  LSHIFTR_CO can be used to zero a
  word and simultaneously move the sign bit to the X flag, ASHIFTR_CO can
  be used to propagate the sign bit to the whole word and to the X flag.
  Useful?

* Model the exact timing, i.e., instruction overlap, superscalar issue,
  etc.  Requires modelling the CPU internal function units.

* `386: bt, clc, cmc, cdq[0->1], lea, shld, shrd, stc.

* Make the instruction description cleaner.  Something of this kind would
  be great:

  88k:
	{ADD,		"addu		%d{r},%1{r,0},%2{r,[0-FFFF]}"},
	{ADD_CI,	"addu.ci	%d{r},%1{r,0},%2{r,[0-FFFF]}"},
	...

  sparc:
	{ADD,		"add		%d{r},%1{r,0},%2{r,[-1000,+FFF]"},
	{ADD_CI,	"addx		%d{r},%1{r,0},%2{r,[-1000,+FFF]}"},
	...

  We would need a tool to extract the information and generate a 'synth'
  function.  (That instructionn description format would be useful to
  assemblers, disassemblers, and simulators too.)

* Include a 'synth' function for several targets in one gso binary.
  Have a command line option -t<target> select which one to use.
