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From: Douglas Weber <dweber@aldon.com>
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Subject: Re: AS/400 guess
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Date: Wed, 17 Nov 1999 21:19:01 GMT
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OK let me try to answer some of your guesses(See Soltis for better
description)

Alt wrote:

> Day.
>
> Let my try to guess how IBM's microcode works (in AS/400).
>
> Most intersting thing in AS/400 is a layer between hardware and
> and software. As I guess, such layer (M-layer) looking like an logic
> machine
> from the point of view of other software (operation sysytem and
> applications).
> Such machine have its native instruction set (and perhaps device
> controll
> specification).

Yes called the MI layer.  Note is is a little violated with the newer
languages, but the traditional MI machine is under very tight control and
extensively documented.  There are NO places where the super-MI accesses the
sub-MI without using designed interfaces.

> Such virtual instruction set (V-set) is different from
> instructions set of real machine (real hardware layer).

Really different.  See especially the change from IMPI to PowerPC
instruction sets. Same MI worked for both.

>
> Real machine have its own instruction (R-set) set device specification
> memory
> configuration.
> Task of such middle layer (M-layer) provide execution virtual machine
> code
> (V-code) at the real machine code (R-code).
>
> How it works ? Simple emulation
> of virtual machine can not take any serious result becouse it's too
> slow.
> (AS/400 works enough quick.)
>
> I think that it work in such way. V-code comes to M-layer as a sequence
> of
> instructions. V-code instructions might be:
>           1. mathematical/logical
>           2. branche/jump (go to)
>           3. memory access
> and perhaps   4. some special controll instructions.
> M-layer its a program which takes instruction of V-code and tranforme it
> to
> instruction of R-code, then it place it in real memory.

Well yes.  The CRTPGM MI instruction(and OX translator in general) takes an
MI program(in binary code) and produces an actual executable program from
this.  The program is in the target machine instruction set.  It was this
ability that allowed the PowerPC based hardware to just slip in under the
IMPI code.  MI code that maintains visibility keeps the MI instruction
stream and so can be re-translated at will.

There is one mistake here, that is causing your subsequent problems.  This
translation is not done every time the program is loaded.  It is done only
once, usually by the compiler after the source to MI is done.  If there is
no such action done, you do not have an program, in the sense of something
that OS/400 will cause to be executed.

> Handling of
> mathematic
> instruction relative simple task biggest problem here place in a
> registers
> variable value, but it have few participial solutions, and let me miss
> it.
> Other thing with "go to" and "memory access" instructions of V-code.
> We can not tranform V-code to R-code with pointers of jump points and
> memory
> blocks, becouse we loss relative value of such pointers dure assembling
> of
> code.

The above description is a little confusing to me.  I think you are assuming
that somehow there is a link at execution between the executing instruction
stream and the MI code.  This is not true(there are debug links around for
access to the MI code and hence to the source, but they are pure overhead
and data at execution). Once the MI is translated, it is memory image of
executing code.  Simple safe MI instructions, like add two integers, are
represented by instructions sequences. Complex instructions, like create a
DataBase cursor, are represented by calls to sub-MI code that validates
actions and performs it.

Also note, this is once place where the single level store is very helpful.
There is no load phase where relative addresses in the saved version are
converted to real memory address as assigned at execution.  The output of
the translation goes directly to an address since the program will reside in
a Segment(SID) which is a range of addresses(actually multiple SIDs if
needed with appropriate linkage). If the program is recreated, a new SID is
assigned and the translation goes directly into this.

> I tell value of pointer in assembler's language defines dure
> assebling
> of code depending by it length. Length of V- and R-code not same (in
> general)
> as a result dure transcoding true pointers losses.
> I think that pointer restore provides by the next algorithme:
>
> =begin
> =if argument of this algorythm exist in database goto position in R-code
> stored in database.
>
> =else
>
> =set begin of V-code equal to argument of this algorythme
> =until V-code instruction is not "goto" instruction.
>     {
>         =take instruction[s] of V-code
>         =trancode V to R
>         =place R-code instruction[s]
>     }
>
> // "goto" - instruction processing
>
>     =place jump to this algorythme with value
>                 of V-code address like an formal argumente into result
> R-code.
>
> =store in database argument and begin of R-code generated in current
> call of
>   this algorythme.
>
> =goto begin of R-code currently generated.
> =end
>
> Other thing provided by similar algorythmes.
>

As I said above, it turns out these fancy algorithms are not needed.  The
translator can produce code that can run with no interpreter or emulator
action required.  Just possibly massive segments of kernel like code.

Doug Weber

>
> --Alternative (Myhailo Mytrofanov)
> Kyiv, Ukraine
>
> [I hate my f'n country. Thay say that 's all right by do not think so.
> Tell me where 's my job ? house ? education ? chieldhood ?
> Isn't thay mast to respect ?]
>
> [Speack you EuROPEAN ?]

