Using the Electric VLSI Design System

Chapter XI: MENU SUMMARY

| ## 10: The Tools Menu |

This menu is a collection of submenus that controls the different analysis and synthesis tools in Electric. For analysis, there are Design-Rule Checkers, a simulator, many simulation interfaces, and a network consistency checker. For synthesis, there are routers, PLA generators, a VHDL compiler, and a silicon compiler place-and-route system.

### DRC [9-2]

| This submenu controls the design-rule checkers. There is an incremental system which watches all design and displays warnings where appropriate. There is also a hierarchical checker and an interface to the Dracula DRC system.

| Hierarchical Check | This checks the current facet hierarchically (all geometry is checked, all the way down the hierarchy).
| Nonhierarchical Check | This command checks the current facet nonhierarchically (only geometry in the current facet is checked, not in any subfacets).
| DRC Options... | This command provides a way to examine and modify the design rules (by using the "From layer" and "To layer" areas). In addition, you can control whether or not the incremental DRC is running, choose to interactively highlight errors, and edit the Dracula design rules.
| Clear Ignored Errors | This command tells the design-rule checker to throw away the list of ignored errors that may have accumulated.
| Write Dracula Deck | This command tells the design-rule checker to produce an input deck for the Dracula design-rule checker. At the current time, only layout in the MOSIS CMOS (mocmos) technology can be checked in this manner. However, with the "Edit Dracula Deck" button of the DRC Options... dialog, rule sets may be defined for any technology.

### Simulation [10-1] [10-2]

| This submenu controls the gate-level simulator in Electric. You can control simulation, move up and down the hierarchy, control test vectors, and set simulation parameters.

| Simulate... | This command causes the current facet to be simulated. If the current facet is not a netlist, and the netlist associated with this facet is missing or out of date, the VHDL compiler is invoked to build a new one. If the current facet is not VHDL, and the VHDL associated with this facet is missing or out of date, it is generated from the schematic or layout. A waveform display is normally shown for viewing signal values.
| Simulation Options... | This command presents a dialog for control of simulation parameters. The "Resimulate each change" item causes each change that is made to the simulation to trigger resimulation and display of the results. The "Auto advance time" item tells the simulator to move the time cursor automatically when a new signal is added to the simulation. The "Multistate display" check tells the simulator to show signals in the layout or schematics window with texturing and color to indicate strength. Without this, a simple on/off indication is drawn in the layout or schematics window. The "Show waveform window" check tells the simulator to create a separate window with waveform plots when simulation starts. The maximum number of events to simulate can be changed if you want to extend the simulator's range (and memory usage).
| Annotate Delay Data |
| This command lets you select which of the sets of stimulus data to use. The stimulus data is acquired with the SDF subcommand of the Import command of the File menu.
| Restore Signal Display Order | This command restores the default set of signals in the waveform display, which is useful if they have been rearranged or if some signals were deleted.
| Down Hierarchy... | This command causes the simulation to descend the hierarchy to a lower level so that signals can be viewed there. You will be prompted with a list of lower levels to view.
| Up Hierarchy | This command causes the simulation to ascend to the next higher level of hierarchy.
| Read Vectors from Disk | This command causes a file of test vectors to be read from disk. You will be prompted for the file name.
| Save Vectors to Disk | This command causes the current set of test vectors to be saved to disk. You will be prompted for the file name.
| Clear All Vectors | This command erases all test vectors from the simulation.

### Simulation Interface [9-4]

| This submenu allows input decks to be written for many different simulators. For all except SPICE, only a deck is written. For SPICE, it is possible to read the output back into Electric for display as a plot.

| Write SPICE Deck | This command generates an input deck for the SPICE circuit-level simulator. Since SPICE is not an interactive system, it is necessary to specify inputs and outputs in the circuit. This is done by placing Source and Meter components (from the New Analog Component submenu of the Edit menu), parametrizing them with the actual SPICE message, and connecting them to the circuitry. It is also necessary to specify Transient or DC analysis by placing an appropriate Source component in the facet.
| SPICE Options... | This command allows many SPICE options to be controlled, for example, the SPICE format (SPICE 2, SPICE 3, or HSPICE); the SPICE level (1, 2, or 3); the option of including parasitics in the deck; the use of Electric node names in the deck (SPICE 3 and HSPICE); whether or not to run SPICE and/or read its output after generating the deck (UNIX systems only); where to find model cards (on disk, or use the built-in ones settable with the next command); whether to use a file of trailer cards; per-layer resistance, capacitance, and edge capacitance; overall minimum resistance and capacitance; and whether to use files of SPICE descriptions for any facet in the current library.
| Plot SPICE Listing | This command reads the output of a SPICE run and shows the signals in a waveform window.
| Write VERILOG Deck | This command generates an input deck for the Verilog functional simulator.
| VERILOG Options... | This command generates displays a dialog for controlling Verilog deck generation.
| Add VERILOG Declaration | This command allows you to click in the design and type Verilog declarations that will be inserted into the generated deck.
| Add VERILOG Code | This command allows you to click in the design and type Verilog code that will be inserted into the generated deck.
| FastHenry Arc Info... |
This command presents a dialog for including the currently selected arc in the FastHenry analysis, and for setting options on that arc. You can override the thickness, set the number of subdivisions, set the analysis group, and even set a height for the two arc ends. |
| Write FastHenry Deck... | This command generates a FastHenry deck from the current facet.
| FastHenry Options... | This command presents a dialog of options for FastHenry deck generation. The frequency and multipole options control flags that are placed in the deck. The default thickness and subdivision fields provide values that are used when no overrides are specified for individual arcs.
| Write ESIM Deck | This command generates an input deck for the ESIM switch-level simulator (nMOS only, no timing).
| Write RSIM Deck | This command generates an input deck for the RSIM switch-level simulator (nMOS only).
| Write RNL Deck | This command generates an input deck for the RNL switch-level simulator (nMOS only, Lisp-like interface).
| Write COSMOS Deck | This command generates an input deck for the COSMOS switch-level simulator (MOS only).
| Write MOSSIM Deck | This command generates an input deck for the MOSSIM switch-level simulator (MOS only).
| Write TEGAS Deck | This command generates an input deck for the TEGAS/TEXSIM gate-level simulator.
| Write SILOS Deck | This command generates an input deck for the SILOS simulator.
| Write PAL Deck | This command generates an input deck for the Abel PAL generator/simulator.

### Electrical Rules [9-3]

| This command does Logical Effort analysis, which determines the transistor ratios to use in digital schematic components in order to get optimal circuit speed.

| Analyze Substrate and Well | This command examines the current facet and checks all substrate and well areas for proper electrical rules. The farthest distance from a substrate or well contact to the edge of its implant is shown.
| ERC Options... | This presents a dialog with Electric Rules Checking options. For the substrate and well areas, you can choose to require one contact per area, or only one contact anywhere on the chip. You can also choose to ignore the contacts altogether.

### Network [6-9] [9-6]

| This submenu controls miscellaneous network functions, including a network consistency checking facility.

| Show Network | This command shows the equivalent to the currently highlighted network in all other windows. It also works for network names seleted in a text window. If this facet has been run through the network consistency checker, that information will be used.
| Network Options... | This presents a dialog with network control options. "Unify Power and Ground" indicates that all power and ground ports should be considered to be electrically tied, regardless of their connectivity in the circuit. When not checked, this only happens in schematics, where the Power and Ground nodes appear. "Unify all like-named nets" indicates that all networks with the same name are to be unified, regardless the nature of the circuit. When not checked, only schematic facets have like-named networks electrically connected. "Automatically name networks" requests that all networks be given names if no arc or port name can be found. "Hierarchical NCC" instructs the network consistency checker to examine the contents of facet instances, thus flattening the hierarchy before checking begins. "Use port names in NCC" instructs the network consistency checker to consider port names when doing network consistency checking.
| Do Consistency Check | This command compares the networks in the two facets being displayed.
| Set First Equate | In order to help the network consistency checker, it is possible to explicitly indicate two components from different facets that are equivalent. To do so, select a component from one facet and issue this command. Then select the equivalent component in the other facet and issue the next command.
| Set Second Equate | This command completes the specification of two equivalent components for the consistency checker. The currently highlighted node is recorded as equivalent to the node that was highlighted when the above command was issued.
| Clear Equates | This command erases the list of equivalent components.
| Rip Bus Signals [7-6] | This command takes the currently selected bus wire and adds wire taps for each signal on the bus. The wires run perpendicular to the bus and are labeled with their signal.
| Redo Network Numbering [6-13] | This command is not generally needed but may be useful if you suspect that the network information is incorrect.

### Logical Effort [9-12]

| This command does Logical Effort analysis, which determines the transistor ratios to use in digital schematic components in order to get optimal circuit speed.

| Analyze Facet | This command examines the current facet and annotates all schematic gates with fanout information.
| Analyze Path | This command examines the circuitry between the two highlighted components and annotates the gates with fanout information.
| Set Arc Capacitance... | This command allows you to set a capacitance value on the currently selected arc. This value can be changed by double-clicking and typing a new value. The default capacitance value for unmarked arcs is 1.
| Set Node Effort... | This command allows you to set an overriding logical effort value on the currently selected node. This value can be changed by double-clicking and typing a new value.
| Set Options... |
This command provides options for controlling the Logical Effort tool. The Maximum Stage Gain is used in the Analyze Facet command. The "Display intermediate capacitances" enables the display of capacitance values on arcs in the circuit. The "Highlight components" causes the tool to highlight the active components that it is analyzing. |

### Routing [9-5]

| This submenu controls a number of wire routing facilities.

| Enable Auto-Stitching | This command instructs the router to watch all subsequent layout activity and to place arcs wherever touching nodes create implicit connections. It is useful to issue this command before generating arrays, because the array may produce many implicit connections that this router will make explicit. The menu entry changes to Stop Auto-Stitching to disable the function.
| Auto-Stitch Highlighted Now | This does auto-stitching only in the currently highlighted area. The highlighted area is defined as the bounding rectangle of everything that is highlighted. A more precise way of defining a highlighted area is to use the rectangle select button to drag a rectangle on the screen.
| Enable Mimic-Stitching | This command instructs the router to watch all subsequent layout activity and to automatically create other arcs in similar locations whenever you create one by hand. The menu entry changes to Disable Mimic-Stitching to disable this function.
| Mimic-Stitching Now | This command instructs the router to mimic the last arc that was created. It is not necessary for the Mimic Stitcher to be enabled.
| Maze-Route Selected | This command runs the maze router in the selected area. All occurrences of the Unrouted wire will be replaced with real geometry.
| Maze-Route Facet | This command runs the maze router in the current facet. All occurrences of the Unrouted wire will be replaced with real geometry.
| River-Route | This command runs the river-router in the current facet. All occurrences of the Unrouted wire will be replaced with real geometry.
| Routing Options... | This command provides a dialog for control of the stitching routers.
For the Auto-Stitcher, you can select the type of arc to use (the default is to automatically determine the arc type to use from the ports). |
For the Mimic-Stitcher, you can instruct it to mimic wire deletions as well as creations. The Mimic-Stitcher can also be instructed to relax its rules for mimicing (by default, arcs are mimiced if they run between the same ports on other nodes; however you can request that mimicing happens between any other ports that are the same distance apart as the original arc).
| Unroute | This command takes the currently selected network(s) and converts them to unrouted wires. After this command, you can maze-route or river-route the unrouted wires.
| Get Unrouted Wire | This command selects the unrouted wire so that subsequent wiring commands will use it. This is necessary in order to do maze and river-routing.

### Generation

| This command provides a pad frame generator and two PLA generators. All will run faster if the design-rule checker is turned off first.

| Pad Frame [9-8] | This command prompts for a disk file that describes the placement of pads around a core facet. The file includes information about the library that contains the pads and also the connection between the pads and ports on the core facet.
| nMOS PLA [9-7] | This command prompts for a personality table and generates nMOS layout, complete with power and clocking. See the description of the PLA generator for a sample personality table.
| MOSIS CMOS PLA [9-7] | This command prompts for two personality tables: the AND and the OR tables. It also offers options about the location of inputs and outputs. See the description of the PLA generator for a sample CMOS personality table.

### VHDL Compiler [9-10]

| This submenu provides direct control of the VHDL compiler, which translates VHDL textual descriptions into netlists. Besides controlling which format netlist is generated, it is also possible to determine whether the netlist of the VHDL is to be stored in memory (in a facet) or on disk.

| Compile for Silicon Compiler | This command causes the VHDL in the current facet to be compiled into a netlist for the silicon compiler. If the current facet is not a VHDL view, the VHDL view is used. If VHDL disk files are being used instead of facets, the file "XXX.vhdl" is read, where XXX is the cell name of the current facet. If netlists are being written to disk, the file "XXX.sci" is written.
| Compile for Simulation | This command causes the VHDL in the current facet to be compiled into a netlist for simulation. If the current facet is not a VHDL view, the VHDL view is used. If VHDL disk files are being used instead of facets, the file "XXX.vhdl" is read, where XXX is the cell name of the current facet. If netlists are being written to disk, the file "XXX.net" is written.
| Compile for RNL | This command causes the VHDL in the current facet to be compiled into a RNL simulator netlist. If the current facet is not a VHDL view, the VHDL view is used. If VHDL disk files are being used instead of facets, the file "XXX.vhdl" is read, where XXX is the cell name of the current facet. If netlists are being written to disk, the file "XXX.net" is written.
| Compile for RSIM | This command causes the VHDL in the current facet to be compiled into a RSIM simulator netlist. If the current facet is not a VHDL view, the VHDL view is used. If VHDL disk files are being used instead of facets, the file "XXX.vhdl" is read, where XXX is the cell name of the current facet. If netlists are being written to disk, the file "XXX.net" is written.
| Compile for SILOS | This command causes the VHDL in the current facet to be compiled into a SILOS simulator netlist. If the current facet is not a VHDL view, the VHDL view is used. If VHDL disk files are being used instead of facets, the file "XXX.vhdl" is read, where XXX is the cell name of the current facet. If netlists are being written to disk, the file "XXX.sil" is written.
| VHDL Options... |
This command provides options for controlling whether the VHDL or the Netlist are stored in memory or on disk. Besides the compile subcommands in this menu, the state of these switches also affects the Make VHDL command of the View menu, the Simulate... subcommand of the Simulation command of the Tools menu, and the Get Network for Current Facet subcommand of the Silicon Compiler command of the Tools menu. |
This command also controls the VHDL that is generated from schematics nodes. Each schematics node is shown, along with its regular and negated VHDL symbol (the use of "%d" is replaced by the number of inputs on the gate).
| Select Behavioral Library... | When compiling for simulation, behavioral models will be included if they are found in the current library. This command allows an alternate library to be searched for the models. Note that each model can be found in the "netlist-als-format" view of an appropriately named cell.

### Silicon Compiler [9-9]

| This submenu is an extensive system for placing and routing standard cell libraries from a structural VHDL description. Simply run each command in sequence: select a library, set options, obtain a netlist, place, route, and make Electric layout.

| Read MOSIS CMOS Submicron Library | This command requests that the MOSIS CMOS Submicron standard cell library be used. This cell library is not guaranteed to be correct and exists only for illustration purposes. See the "Silicon Compiler" section of Chapter 9 for a description of the cells in this library.
| Silicon Compiler Options... | This command presents a dialog that allows the setting of various parameters for the silicon compilation process.
| Get Network for Current Facet | This command gets a netlist for the current facet. If the current facet is not a netlist, and the netlist associated with this facet is missing or out of date, the VHDL Compiler will be used to create a netlist. If the current facet is not VHDL, and the VHDL associated with this facet is missing or out of date, the VHDL will be generated from a schematic.
| Do Placement | This command computes the placement of standard cells.
| Do Routing | This command computes the routing among the placed standard cells.
| Make Electric Layout | This command generates final circuitry from the computed placement and routing. The design-rule checker is turned off during this step.
| Issue Special Instructions... | This command allows you to communicate directly with the Silicon Compiler. Only those familiar with the system should do this (the other commands in this submenu handle standard functions without the need to know how the compiler works). If you do issue this command accidentally, use the "quit" command to exit the compiler.

### Compaction [9-11]

| This submenu controls the layout compactor.

| Do Compaction | This command compacts the layout in the current window to design-rule distances. It alternates horizontal and vertical compaction until no additional space can be saved.
| Compaction Options... |
This command presents a dialog that allows you to tell the compactor to spread the circuit where it is too close for the design rules. |

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