Using the Electric VLSI Design System

Chapter IX: TOOLS

| ## 2: Design-Rule Checking |

The design-rule checker is a collection of tools for checking the spacing of a circuit. By default, there is an incremental design-rule checker that watches over the editing session and displays error messages when the geometry is incorrect. A hierarchical checker examines the layout hierarchically. In addition to that, it is possible to prepare input decks for Dracula, an external design-rule checker.

### Incremental DRC

The incremental design-rule checker is always running, examining your work, and issuing error messages when an error is detected. Three types of errors are detected by the design-rule checker. Spacing errors are caused by geometry that is too close, but not connected. Notch errors are caused by geometry that is too close, but connected. Minimum size errors are caused by geometry that is too small.

In addition to examining geometry, the design-rule checker uses connectivity information to help it find violations. This use of network information helps the designer to debug circuit connectivity. For example, if two overlapping nodes are not joined by an arc, they may be considered to be in violation, even if their geometry looks right. This is because the checker knows what is connected and has a separate set of rules for such situations.

The user should be warned that the incremental design-rule checker does not examine hierarchy. This means that if a facet instance is used in a circuit, the design-rule checker does not examine its contents to see how that interacts with other layout surrounding the instance. To check the complete hierarchy, use the Hierarchical Check subcommand.

To control the DRC and set the rules, use the DRC Options... subcommand of the DRC command of the Tools menu.

By default, the incremental design-rule checker is on. To turn it off, uncheck the "On" checkbox in the "Incremental DRC" section. While the tool is off, Electric keeps track of all facets that change. When the tool is turned back on it rechecks all of those changed facets. Thus, the design-rule checker can be made into a "batch" tool by keeping it off until circuit layout is complete.

The incremental design-rule checker has two styles in which it can work. By default, each violation is simply displayed in the messages window, and no acknowledgement is expected. If you check "Highlights errors" in the dialog, it causes violations to be highlighted and the system to awaits further instructions. Uncheck the item to disable this interactive mode.

| While in the interactive mode, a dialog will be presented when any design-rule violation is detected. The possible responses to this dialog are to continue checking (the "OK" button), to remember this violation and ignore it in subsequent checking (the "Ignore this error" button), to continue checking silently (the "Continue Silently" button), and to terminate checking (the "Stop Checking" button). The "Continue Silently" and "Stop Checking" buttons can apply to the current batch of errors ("For now") or permanently (this affects the settings in the "DRC Options" dialog).

The dialog also allows you to examine and modify the spacing limits. You can select a "For layer", and set rules for that layer. These rules include the minimum width, and spacing rules to other layers. Select either the "Unconnected To:" or the "Connected To:" buttons to choose the appropriate design rule set. The "Factory Reset" button restores all rules to the original set built into Electric.

Because errors are not repeated once they are detected, it is useful to recheck an entire facet to see what errors remain. Use the Recheck Facet subcommand to run the design-rule checker over the current facet. The command Recheck Entire Facet works in the same way, except that any violations that were ignored (with the "Ignore this error" button) are also considered (the list of ignored violations is deleted).

### Hierarchical DRC

The hierarchical design-rule checker uses the same rules and techniques as the incremental checker, but it is able to check across levels of hierarchy. To run it, use the Hierarchical Check subcommand of the DRC command of the Tools menu.

After analysis of the circuit, you can review the errors by typing ">" and "<" to step to the next and previous error that was found, or by typing "&" to repeat the current error.

After a facet has passed Hierarchical DRC with no errors, it is tagged with the current date. In subsequent runs of the Hierarchical DRC, if the facet has not been modified since that date, it is not rechecked. If you wish to force all facets to be rechecked, use the "Clear valid DRC dates" button in the DRC Options... dialog. To see which facets have passed Hierarchical DRC, use the Facet Description subcommands of the Facet Information command of the Facets menu.

Another way to speed up Hierarchical DRC is to check the "Just 1 error per facet" entry in the DRC Options... dialog. This tells the system to stop checking a facet after the first error has been found. By using this option, you can more quickly determine which facets in the design are correct, without knowing exactly where the errors lie. Then, you can go to the facets with errors and do a more complete check.

If the "Use dialog" is checked in the "Hierarchical DRC" section of the DRC Options... dialog, then a dialog will be presented for doing hierarchical DRC.

Select the "Check" button to begin checking. When the check is done, you can see the errors with the "Show Next Error" and "Show Prev Error" buttons. Use the "Done" button to terminate the checking. |

### Dracula DRC

Another design-rule checking facility that is available in Electric is an interface with the Dracula design-rule checker. This interface requires a circuit description and a set of design rules. Electric knows the design-rules (currently only for the MOSIS CMOS technology) and is able to generate the proper circuit description (a CIF file). To generate these files, use the Write Dracula Deck subcommand.

To see the set of Dracula design rules for the current technology, use the "Edit Dracula Deck" button of the DRC Options... subcommand. This will display the rules in an edit window. The rules must contain the lines: "PRIMARY =" and "INDISK = " so that the deck generator can substitute the proper file names.

Note that since only the "mocmos" technology has valid design rules, this command will present an empty window when run in other technologies. However, you can create your own design-rules for any technology. To do this, follow these steps:

- Use the Change Current Technology... command from the Technology menu to switch to the "mocmos" technology.
- Edit the rules using this command.
- Select everything and use the Copy command of Edit menu to copy them.
- Close the text editing window.
- Use the Change Current Technology... command from the Technology menu to switch to the desired technology.
- Edit the rules with this command, which displays a blank editing window.
- Use the Paste command of the Edit menu to recover the MOSIS CMOS rules.

You can now edit these rules, and they will be saved with your options.

To help guide the Dracula design-rule checker, a "cloaking" layer can be placed over areas that are not to be examined. This cloaking layer is created by using the DRC Exclusion subcommand of the New Special Object command of the Edit menu. The node that is placed produces a layer called "DRC" in the Dracula file, which causes the circuitry underneath to be ignored.

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