Using the Electric VLSI Design System

Chapter VII: DESIGN ENVIRONMENTS

| ## 5: The MOSIS CMOS Submicron Technology |

The MOSIS CMOS submicron technology describes a scalable CMOS process that is fabricated by the MOSIS project of the University of Southern California. To obtain this technology, use the Change Current Technology... command of the Technology menu and select "mocmossub".

This technology defaults to 4 metal layers (shown here), but can also be changed so that it uses anywhere from 2 to 6 layers of metal. This is done with the Technology Options... command of the Technology menu and changing the "Metal layers" field in the "MOSOS CMOS Submicron" section.

By default, this technology describes a p-well process. However, it is possible to switch to an n-well process by using the Technology Options... command of the Technology menu and checking the "Switch N and P Well" button in the "MOSOS CMOS Submicron" section. This command switches layer usage and renames the transistors, contacts, and arcs so that an n-well technology is in effect.

Be warned that Electric always starts up with this as a p-well technology. Therefore, if you have switched to n-well and created a library, you must switch each time you rerun the system before reading that library. The best solution to this situation is to always use the default p-well version of the technology and only switch to n-well before chip fabrication.

Finally, the technology can display with "stick figures" by using the Technology Options... command of the Technology menu and checking the "Stick Figures" button in the "MOSOS CMOS Submicron" section.

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