Using the Electric VLSI Design System

Chapter VII: DESIGN ENVIRONMENTS

| ## 4: The MOS Technologies |

There are both nMOS and CMOS technologies available in Electric, with many different design rules. Use the Change Current Technology... command of the Technology menu to select one.

There is one nMOS technology: "nmos" (the specifications used in the Mead and Conway textbook).

There are many more CMOS technologies available. The most basic is "cmos", which uses an idealized set of design-rules from a paper by Griswold. The "mocmos" process has double metal with MOSIS design rules. The "mocmos2" process has double metal and double polysilicon. The "mocmossub" process has double polysilicon and up to 6 layers of metal with submicron rules (this is the default technology, and it is described more fully in the next section). There is even "rcmos", which uses round geometry!

| Each MOS technology has two transistors (enhancement and depletion in nMOS technologies, n and p in CMOS). These nodes can have serpentine paths by highlighting them and using the Outline Edit command of the Edit menu.

Although individual MOS nodes and arcs have the proper amount of implant around them, a collection of such objects may result in an irregular implant boundary. To clean this up, you can place pure-layer nodes of implant that neatly cover the implant area. Also, you can do this automatically with the Cover Implants subcommand of the Cleanup Facet command of the Edit menu.

| Previous |  |  | Table of Contents |  | Next |