\newcommand{\notthecase}[1]{it is not the case that #1}
\newcommand{\Variant}[1]{#1 is implemented}
\newcommand{\NotVariant}[1]{it is not the case that #1 is implemented}
\newcommand{\flag}[1]{By construction, #1}
\newcommand{\assert}[1]{By construction, #1}
%
%
%
\newcommand{\anyevent}[1]{#1 is any event}
\newcommand{\anyrel}[2]{#1 and #2 are any events}

\newcommand{\transitive}[3]{there exists a chain of #1 from #2 to #3}
\newcommand{\intervening}[4]{there exists a #1 in #2 between #3 and #4}

\newcommand{\includedname}{included in}
\newcommand{\included}[2]{#1 is included in #2}
\newcommand{\includedemph}[2]{#1 is \emph{included in} #2}
\newcommand{\sameloc}[2]{#1 and #2 are to the Same Location}

\newcommand{\sca}[2]{#1 belongs to the same single-copy-atomic class as #2}
\newcommand{\po}[2]{#1 appears in program order before #2}

\newcommand{\coemph}[2]{#1 is \emph{Coherence-write-before} #2}
\newcommand{\fr}[2]{#1 Reads-before #2}
\newcommand{\rf}[2]{#2 Reads-from-memory #1}
\newcommand{\rfi}[2]{#2 Reads-from-internal #1}
\newcommand{\rfreg}[2]{#2 Reads-from-register #1}
\newcommand{\rmw}[2]{#1 and #2 form a successful Read-Modify-Write pair}
\newcommand{\DATA}[2]{#1 affects the data value written by #2}
\newcommand{\ADDR}[2]{#1 affects the address of the Location accessed by #2}
\newcommand{\sameinstance}[2]{#1 and #2 are generated by the same instruction}
\newcommand{\sm}[2]{\sameinstance{#1}{#2}}
\newcommand{\si}[2]{\sameinstance{#1}{#2}}
\newcommand{\sameEffect}[2]{#1 and #2 are the same Effect}
\newcommand{\ext}[2]{#1 and #2 are from different Processing Elements}

%
\newcommand{\ME}{Memory Effect}
\newcommand{\MWE}{Memory Write Effect}
\newcommand{\MRE}{Memory Read Effect}
\newcommand{\M}[1]{#1 is a \ME{}}
\newcommand{\W}[1]{#1 is a \MWE{}}
\newcommand{\R}[1]{#1 is a \MRE{}}
\renewcommand{\_}{any Effect}
\newcommand{\B}[1]{#1 is a Branching Effect}
\newcommand{\BCC}[1]{#1 is a Conditional Branching Effect}
\newcommand{\FAULT}[1]{#1 is a Fault Effect}
\newcommand{\NoRet}[1]{#1 is generated by an instruction whose destination register is WZR or XZR}

\newcommand{\RWE}{Register Write Effect}
\newcommand{\RRE}{Register Read Effect}
\newcommand{\RRWEs}{Register Read and Write Effects}

\newcommand{\Wreg}[1]{#1 is a \RWE{}}
\newcommand{\Rreg}[1]{#1 is a \RRE{}}

\newcommand{\RREof}[1]{the \RRE{} of #1}
\newcommand{\RWEof}[1]{the \RWE{} of #1}

%
\newcommand{\memloc}[1]{the Memory Location #1}
\newcommand{\tagloc}[1]{the Tag Location #1}
\newcommand{\reg}[1]{the Register #1}

%
%

\newcommand{\Exp}[1]{#1 is an Explicit Effect}
\newcommand{\ExpMREof}[1]{the Explicit \MRE{} of #1}
\newcommand{\ExpMWEof}[1]{the Explicit \MWE{} of #1}
\newcommand{\ExpM}[1]{#1 is an Explicit \ME{}}
%
\newcommand{\ExpW}[1]{#1 is an Explicit \MWE{}}
\newcommand{\ExpR}[1]{#1 is an Explicit \MRE{}}

\newcommand{\NExp}[1]{#1 is an Implicit Effect}
\newcommand{\Imp}[1]{\NExp{#1}}
\newcommand{\ImpM}[1]{#1 is an Implicit Memory Effect}
\newcommand{\ImpW}[1]{#1 is an Implicit Memory Write Effect}
\newcommand{\ImpR}[1]{#1 is an Implicit Memory Read Effect}

\newcommand{\Tag}[1]{#1 is a Tag Effect}
\newcommand{\TagCheck}[1]{#1 is a TagCheck Effect}
\newcommand{\ExpTagMRE}{Explicit Tag \MRE{}}
\newcommand{\ExpTagMWE}{Explicit Tag \MWE{}}
\newcommand{\ImpTagMRE}{Implicit Tag \MRE{}}
\newcommand{\ImpTagMWE}{Implicit Tag \MWE{}}
\newcommand{\ImpTagMREof}[1]{the \ImpTagMRE{} of #1}
\newcommand{\ImpTagMWEof}[1]{the \ImpTagMWE{} of #1}
\newcommand{\ImpTagM}[1]{#1 is an Implicit Tag Memory Effect}
\newcommand{\ImpTagW}[1]{#1 is an \ImpTagMWE{}}
\newcommand{\ImpTagR}[1]{#1 is an \ImpTagMRE{}}

\newcommand{\ImpTTDM}[1]{#1 is an Implicit TTD Memory Effect}
\newcommand{\ImpTTDW}[1]{#1 is an Implicit TTD Memory Write Effect}
\newcommand{\HU}[1]{#1 is a Hardware Update Effect}
\newcommand{\ImpTTDR}[1]{#1 is an Implicit TTD Memory Read Effect}

\newcommand{\ImpInstrM}[1]{#1 is an Implicit Instruction Memory Effect}
\newcommand{\ImpInstrW}[1]{#1 is an Implicit Instruction Memory Write Effect}
\newcommand{\ImpInstrR}[1]{#1 is an Implicit Instruction Memory Read Effect}

\newcommand{\ISB}[1]{#1 is an ISB Effect}
\newcommand{\EXCENTRY}[1]{#1 is an Exception Entry Effect}
\newcommand{\EXCRET}[1]{#1 is an Exception Return Effect}
\newcommand{\EXCENTRYIFB}[1]{#1 is an Exception Entry Instruction Fetch Barrier Effect}
\newcommand{\EXCRETIFB}[1]{#1 is an Exception Return Instruction Fetch Barrier Effect}
\newcommand{\IFB}[1]{#1 is an Instruction Fetch Barrier Effect}

\newcommand{\A}[1]{#1 is an Explicit \ME{} generated by an instruction with Acquire semantics}
\newcommand{\Q}[1]{#1 is an Explicit \ME{} generated by an instruction with AcquirePC semantics}
\newcommand{\REL}[1]{#1 is an Explicit \ME{} or a Fault Effect and generated by an instruction with Release semantics}
\newcommand{\rangeAamoL}[1]{#1 is an Explicit \MWE{} and is generated by an atomic instruction with both Acquire and Release semantics}

\newcommand{\DMBFULL}[1]{#1 is a DMB FULL Effect}
\newcommand{\DMBSY}[1]{#1 is a DMB SY Effect}
\newcommand{\DMBST}[1]{#1 is a DMB ST Effect}
\newcommand{\DMBLD}[1]{#1 is a DMB LD Effect}
\newcommand{\DSBFULL}[1]{#1 is a DSB FULL Effect}
\newcommand{\DSBSY}[1]{#1 is a DSB SY Effect}
\newcommand{\DSBST}[1]{#1 is a DSB ST Effect}
\newcommand{\DSBLD}[1]{#1 is a DSB LD Effect}
\newcommand{\TLBI}[1]{#1 is a TLBI Effect}
\newcommand{\CTLBI}[1]{#1 is a Completed TLBI Effect}
\newcommand{\invscope}[2]{#1 is in the Invalidation Scope of #2}
\newcommand{\invscopeemph}[2]{#1 is \emph{in the Invalidation Scope of} #2}
\newcommand{\DCCVAU}[1]{#1 is a DC CVAU Effect}
\newcommand{\IC}[1]{#1 is an IC Effect}
\newcommand{\ICIVAU}[1]{#1 is an IC IVAU Effect}

\newcommand{\Fault}[1]{#1 is a Fault Effect}
\newcommand{\TagCheckFAULT}[1]{#1 is a TagCheck Fault Effect}
\newcommand{\TagCheckEXCENTRY}[1]{#1 is a TagCheck Fault Effect that generates a synchronous exception}
\newcommand{\MMU}[1]{#1 is an MMU Effect}
\newcommand{\MMUFAULT}[1]{#1 is an MMU Fault Effect}
\newcommand{\TLBUncacheableFAULT}[1]{#1 is a TLBUncacheable Fault Effect}

%
\newcommand{\amo}{an atomic operation}
\newcommand{\lxsx}{a successful Load-Exclusive/Store-Exclusive pair}

%
\newcommand{\iicodataname}{Intrinsic Data Dependency}
\newcommand{\iicodata}[2]{there is an \iicodataname{} from #1 to #2}
\newcommand{\iicodataemph}[2]{there is an \emph{\iicodataname{}} from #1 to #2}
\newcommand{\iicoordername}{Intrinsic Order Dependency}
\newcommand{\iicoorder}[2]{there is an \iicoordername{} from #1 to #2}
\newcommand{\iicoorderemph}[2]{there is an \emph{\iicoordername{}} from #1 to #2}
\newcommand{\iicoctrlname}{Intrinsic Control Dependency}
\newcommand{\iicoctrl}[2]{there is an \iicoctrlname{} from #1 to #2}
\newcommand{\iicoctrlemph}[2]{there is an \emph{\iicoctrlname{}} from #1 to #2}

\newcommand{\dtrmname}{Dependency through registers and memory}
\newcommand{\dtrm}[2]{there is a \dtrmname{} from #1 to #2}
\newcommand{\dtrmemph}[2]{there is a \emph{\dtrmname{}} from #1 to #2}
\newcommand{\basicdepname}{Basic dependency}
\newcommand{\basicdep}[2]{there is a \basicdepname{} from #1 to #2}
\newcommand{\basicdepemph}[2]{there is a \emph{\basicdepname{}} from #1 to #2}
\newcommand{\dataname}{Data dependency}
\newcommand{\data}[2]{there is a \dataname{} from #1 to #2}
\newcommand{\dataemph}[2]{there is a \emph{\dataname{}} from #1 to #2}
\newcommand{\addrname}{Address dependency}
\newcommand{\addr}[2]{there is an \addrname{} from #1 to #2}
\newcommand{\addremph}[2]{there is an \emph{\addrname{}} from #1 to #2}
\newcommand{\ctrlname}{Control dependency}
\newcommand{\ctrl}[2]{there is a \ctrlname{} from #1 to #2}
\newcommand{\ctrlemph}[2]{there is a \emph{\ctrlname{}} from #1 to #2}


\newcommand{\pickdtrmname}{Pick dependency through registers and memory}
\newcommand{\pickdtrm}[2]{there is a \pickdtrmname{} from #1 to #2}
\newcommand{\pickdtrmemph}[2]{there is a \emph{\pickdtrmname{}} from #1 to #2}
\newcommand{\pickbasicdepname}{Pick Basic dependency}
\newcommand{\pickbasicdep}[2]{there is a \pickbasicdepname{} from #1 to #2}
\newcommand{\pickbasicdepemph}[2]{there is a \emph{\pickbasicdepname{}} from #1 to #2}
\newcommand{\pickdatadepname}{Pick Data dependency}
\newcommand{\pickdatadep}[2]{there is a \pickdatadepname{} from #1 to #2}
\newcommand{\pickdatadepemph}[2]{there is a \emph{\pickdatadepname{}} from #1 to #2}
\newcommand{\pickaddrdepname}{Pick Address dependency}
\newcommand{\pickaddrdep}[2]{there is a \pickaddrdepname{} from #1 to #2}
\newcommand{\pickaddrdepemph}[2]{there is a \emph{\pickaddrdepname{}} from #1 to #2}
\newcommand{\pickctrldepname}{Pick Control dependency}
\newcommand{\pickctrldep}[2]{there is a \pickctrldepname{} from #1 to #2}
\newcommand{\pickctrldepemph}[2]{there is a \emph{\pickctrldepname{}} from #1 to #2}
\newcommand{\pickdepname}{Pick dependency}
\newcommand{\pickdep}[2]{there is a \pickdepname{} from #1 to #2}
\newcommand{\pickdepemph}[2]{there is a \emph{\pickdepname{}} from #1 to #2}

%
\newcommand{\tcibname}{Tag-check-intrinsically-before}
\newcommand{\tcib}[2]{#1 is Tag-check-intrinsically-before #2}
\newcommand{\tcibemph}[2]{#1 is \emph{Tag-check-intrinsically-before} #2}
\newcommand{\tribname}{Translation-intrinsically-before}
\newcommand{\trib}[2]{#1 is Translation-intrinsically-before #2}
\newcommand{\tribemph}[2]{#1 is \emph{Translation-intrinsically-before} #2}
\newcommand{\fibname}{Fetch-intrinsically-before}
\newcommand{\fib}[2]{#1 is Fetch-intrinsically-before #2}
\newcommand{\fibemph}[2]{#1 is \emph{Fetch-intrinsically-before} #2}

\newcommand{\sameoa}[2]{#1 and #2 have the Same Output Address}
\newcommand{\sameloworderbits}[2]{#1 and #2 have the Same Low Order Bits}
\newcommand{\valoc}[2]{#1 and #2 are to the Same Virtual Address}
\newcommand{\lrsname}{a Local read successor of}
\newcommand{\lrs}[2]{#2 is a Local read successor of #1}
\newcommand{\lwfsname}{a Local write or MMU Fault successor of}
\newcommand{\lwfs}[2]{#2 is a Local write or MMU Fault successor of #1}
% \edef\povaloc#1#2{\po{#1}{#2} and \valoc{#1}{#2}}
\newcommand{\povaloc}[2]{\po{#1}{#2} and \valoc{#1}{#2}}

\newcommand{\samereg}[2]{#1 and #2 are to the Same Register}
\newcommand{\sameval}[2]{#2 takes its data from #1}
\newcommand{\scl}[2]{#1 and #2 are to the Same Cache Line}
\newcommand{\dobname}{Dependency-ordered-before}
\newcommand{\dob}[2]{#1 is \dobname{} #2}
\newcommand{\dobemph}[2]{#1 is \emph{\dobname{}} #2}
\newcommand{\pobname}{Pick-ordered-before}
\newcommand{\pob}[2]{#1 is \pobname{} #2}
\newcommand{\pobemph}[2]{#1 is \emph{\pobname{}} #2}
\newcommand{\aobname}{Atomic-ordered-before}
\newcommand{\aob}[2]{#1 is \aobname{} #2}
\newcommand{\aobemph}[2]{#1 is \emph{\aobname{}} #2}
\newcommand{\bobname}{Barrier-ordered-before}
\newcommand{\bob}[2]{#1 is \bobname{} #2}
\newcommand{\bobemph}[2]{#1 is \emph{\bobname{}} #2}
\newcommand{\DSBobname}{DSB-ordered-before}
\newcommand{\DSBob}[2]{#1 is DSB-ordered-before #2}
\newcommand{\DSBobemph}[2]{#1 is \emph{DSB-ordered-before} #2}
\newcommand{\IFBobname}{Instruction-fetch-barrier-ordered-before}
\newcommand{\IFBob}[2]{#1 is Instruction-fetch-barrier-ordered-before #2}
\newcommand{\IFBobemph}[2]{#1 is \emph{Instruction-fetch-barrier-ordered-before} #2}
\newcommand{\TLBIbname}{TLBI-before}
\newcommand{\TLBIb}[2]{#1 is \TLBIaname{} #2}
\newcommand{\TLBIbemph}[2]{#1 is \emph{\TLBIaname{}} #2}
\newcommand{\TLBIaname}{TLBI-after}
\newcommand{\TLBIa}[2]{#1 is \TLBIbname{} #2}
\newcommand{\TLBIaemph}[2]{#1 is \emph{\TLBIbname{}} #2}
\newcommand{\DCbname}{DC-before}
\newcommand{\DCb}[2]{#1 is \DCaname{} #2}
\newcommand{\DCbemph}[2]{#1 is \emph{\DCaname{}} #2}
\newcommand{\DCaname}{DC-after}
\newcommand{\DCa}[2]{#1 is \DCbname{} #2}
\newcommand{\DCaemph}[2]{#1 is \emph{\DCbname{}} #2}
\newcommand{\ICbname}{IC-before}
\newcommand{\ICb}[2]{#1 is \ICaname{} #2}
\newcommand{\ICbemph}[2]{#1 is \emph{\ICaname{}} #2}
\newcommand{\ICaname}{IC-after}
\newcommand{\ICa}[2]{#1 is \ICbname{} #2}
\newcommand{\ICaemph}[2]{#1 is \emph{\ICbname{}} #2}
\newcommand{\TLBIcbname}{TLBI-coherence-before}
\newcommand{\TLBIcb}[2]{#1 is \TLBIcaname{} #2}
\newcommand{\TLBIcbemph}[2]{#1 is \emph{\TLBIcaname{}} #2}
\newcommand{\TLBIcaname}{TLBI-coherence-after}
\newcommand{\TLBIca}[2]{#1 is \TLBIcbname{} #2}
\newcommand{\TLBIcaemph}[2]{#1 is \emph{\TLBIcbname{}} #2}
\newcommand{\ICcbname}{IC-coherence-before}
\newcommand{\ICcb}[2]{#1 is \ICcaname{} #2}
\newcommand{\ICcbemph}[2]{#1 is \emph{\ICcaname{}} #2}
\newcommand{\ICcaname}{IC-coherence-after}
\newcommand{\ICca}[2]{#1 is \ICcbname{} #2}
\newcommand{\ICcaemph}[2]{#1 is \emph{\ICcbname{}} #2}

\newcommand{\TLBIaftername}{\TLBIaname}
\newcommand{\TLBIafter}[2]{\TLBIa{#1}{#2}}
\newcommand{\ICaftername}{\ICaname}
\newcommand{\ICafter}[2]{\ICa{#1}{#2}}
\newcommand{\DCafter}[2]{\DCa{#1}{#2}}

\newcommand{\cbname}{Coherence-before}
\newcommand{\cb}[2]{#1 is \caname{} #2}
\newcommand{\cbemph}[2]{#1 is \emph{\caname{}} #2}
\newcommand{\caname}{Coherence-after}
\newcommand{\ca}[2]{#1 is \cbname{} #2}
\newcommand{\caemph}[2]{#1 is \emph{\cbname{}} #2}


\newcommand{\lobname}{Locally-ordered-before}
\newcommand{\lob}[2]{#1 is Locally-ordered-before #2}
\newcommand{\lobemph}[2]{#1 is \emph{Locally-ordered-before} #2}
\newcommand{\picklobname}{Pick-locally-ordered-before}
\newcommand{\picklob}[2]{#1 is Pick-locally-ordered-before #2}
\newcommand{\picklobemph}[2]{#1 is \emph{Pick-locally-ordered-before} #2}
\newcommand{\localhwreqsname}{Locally-hardware-required-ordered-before}
\newcommand{\localhwreqs}[2]{#1 is Locally-hardware-required-ordered-before #2}
\newcommand{\localhwreqsemph}[2]{#1 is \emph{Locally-hardware-required-ordered-before} #2}

\newcommand{\hazobname}{Hazard-ordered-before}
\newcommand{\hazob}[2]{#1 is Hazard-ordered-before #2}
\newcommand{\hazobemph}[2]{#1 is \emph{Hazard-ordered-before} #2}
\newcommand{\Exphazobname}{Explicitly-hazard-ordered-before}
\newcommand{\Exphazob}[2]{#1 is Explicitly-hazard-ordered-before #2}
\newcommand{\Exphazobemph}[2]{#1 is \emph{Explicitly-hazard-ordered-before} #2}
\newcommand{\TTDreadobname}{TTD-read-ordered-before}
\newcommand{\TTDreadob}[2]{#1 is TTD-read-ordered-before #2}
\newcommand{\TTDreadobemph}[2]{#1 is \emph{TTD-read-ordered-before} #2}
\newcommand{\TLBIobname}{TLBI-ordered-before}
\newcommand{\TLBIob}[2]{#1 is TLBI-ordered-before #2}
\newcommand{\TLBIobemph}[2]{#1 is \emph{TLBI-ordered-before} #2}
\newcommand{\Instrreadobname}{Instruction-read-ordered-before}
\newcommand{\Instrreadob}[2]{#1 is Instruction-read-ordered-before #2}
\newcommand{\Instrreadobemph}[2]{#1 is \emph{Instruction-read-ordered-before} #2}
\newcommand{\ICobname}{IC-ordered-before}
\newcommand{\ICob}[2]{#1 is IC-ordered-before #2}
\newcommand{\ICobemph}[2]{#1 is \emph{IC-ordered-before} #2}
\newcommand{\hwreqsname}{Hardware-required-ordered-before}
\newcommand{\hwreqs}[2]{#1 is Hardware-required-ordered-before #2}
\newcommand{\hwreqsemph}[2]{#1 is \emph{Hardware-required-ordered-before} #2}
\newcommand{\obsname}{Observed-by}
\newcommand{\obs}[2]{#1 is Observed-by #2}
\newcommand{\obsemph}[2]{#1 is \emph{Observed-by} #2}
\newcommand{\Expobsname}{Explicitly-Observed-by}
\newcommand{\Expobs}[2]{#1 is Explicitly-Observed-by #2}
\newcommand{\Expobsemph}[2]{#1 is \emph{Explicitly-Observed-by} #2}
\newcommand{\Tagobsname}{Tag-Observed-by}
\newcommand{\Tagobs}[2]{#1 is \Tagobsname{} #2}
\newcommand{\Tagobsemph}[2]{#1 is \emph{\Tagobsname{}} #2}
\newcommand{\TTDobsname}{TTD-Observed-by}
\newcommand{\TTDobs}[2]{#1 is \TTDobsname{} #2}
\newcommand{\TTDobsemph}[2]{#1 is \emph{\TTDobsname{}} #2}
\newcommand{\Instrobsname}{Instruction-Observed-by}
\newcommand{\Instrobs}[2]{#1 is \Instrobsname{} #2}
\newcommand{\Instrobsemph}[2]{#1 is \emph{\Instrobsname{}} #2}
\newcommand{\obname}{Ordered-before}
\newcommand{\ob}[2]{#1 is Ordered-before #2}
\newcommand{\obemph}[2]{#1 is \emph{Ordered-before} #2}

\newcommand{\TLBuncacheablepredname}{a TLBUncacheable-Write-Predecessor of}
\newcommand{\TLBuncacheablepred}[2]{#1 is a TLBUncacheable-Write-Predecessor of #2}
\newcommand{\TLBuncacheablepredemph}[2]{#1 is \emph{a TLBUncacheable-Write-Predecessor of} #2}
\newcommand{\TLBuncacheablesuccname}{a TLBUncacheable-Write-Successor of}
\newcommand{\TLBuncacheablesucc}[2]{#1 is a TLBUncacheable-Write-Successor of #2}
\newcommand{\TLBuncacheablesuccemph}[2]{#1 is \emph{a TLBUncacheable-Write-Successor of} #2}
\newcommand{\HUpredname}{a Hardware-Update-Predecessor of}
\newcommand{\HUpred}[2]{#1 is a Hardware-Update-Predecessor of #2}
\newcommand{\HUpredemph}[2]{#1 is \emph{a Hardware-Update-Predecessor of} #2}
\newcommand{\HUsuccname}{a Hardware-Update-Successor of}
\newcommand{\HUsucc}[2]{#1 is a Hardware-Update-Successor of #2}
\newcommand{\HUsuccemph}[2]{#1 is \emph{a Hardware-Update-Successor of} #2}

%
\newcommand{\byamo}[1]{#1 is generated by \amo\xspace}

\newcommand{\rangelxsx}[1]{#1 is generated by a Store-Exclusive instruction as part of \lxsx}
\newcommand{\rangetribminus}[3]{\ImpTTDR{#1} and \trib{#1}{an Effect #2 such that #3}}

%
\newcommand{\pofetchobname}{Fetch-ordered-before}
\newcommand{\pofetchob}[2]{#1 is Fetch-ordered-before #2}
\newcommand{\pofetchobemph}[2]{#1 is \emph{Fetch-ordered-before} #2}
\newcommand{\posclobname}{Same-Cache-Line-ordered-before}
\newcommand{\posclob}[2]{#1 is Same-Cache-Line-ordered-before #2}
\newcommand{\posclobemph}[2]{#1 is \emph{Same-Cache-Line-ordered-before} #2}
\newcommand{\etsobname}{ETS-ordered-before}
\newcommand{\etsob}[2]{#1 is ETS-ordered-before #2}
\newcommand{\etsobemph}[2]{#1 is \emph{ETS-ordered-before} #2}
\newcommand{\fobname}{Fetch-ordered-before}
\newcommand{\fob}[2]{#1 is Fetch-ordered-before #2}
\newcommand{\fobemph}[2]{#1 is \emph{Fetch-ordered-before} #2}
\newcommand{\irobname}{Implicit-Read-ordered-before}
\newcommand{\irob}[2]{#1 is Implicit-Read-ordered-before #2}
\newcommand{\irobemph}[2]{#1 is \emph{Implicit-Read-ordered-before} #2}
\newcommand{\iobname}{Intrinsically-ordered-before}
\newcommand{\iob}[2]{#1 is Intrinsically-ordered-before #2}
\newcommand{\iobemph}[2]{#1 is \emph{Intrinsically-ordered-before} #2}
\newcommand{\tcbeforename}{Tag-check-before}
\newcommand{\tcbefore}[2]{#1 is Tag-check-before #2}
\newcommand{\tcbeforeemph}[2]{#1 is \emph{Tag-check-before} #2}

\newcommand{\invdomain}[2]{\invscope{#1}{#2}}
\newcommand{\ImpTTD}[1]{\ImpTTDM{#1}}

\newcommand{\TTDreadorderedbefore}[2]{\TTDreadob{#1}{#2}}
\newcommand{\TTDreadorderedbeforeemph}[2]{\TTDreadobemph{#1}{#2}}

\newcommand{\nointerv}[4]{there is no #1 in #2 between #3 and #4}
\renewcommand{\int}[2]{#1 and #2 are from the same Processing Element}
