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                 VL 2014 -- VL Verilog Toolkit, 2014 Edition

                             Failure Tests

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This directory contains various test cases that VL should reject and fail to
translate.

Each test should define a parameter-free module named "top" that has a problem
(or that instantiates a module that has a problem).

The Makefile tries to translate each file, in isolation, using VL, in both
Verilog and SystemVerilog modes.  It instructs VL to ensure that the top module
is not successfully translated.

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