# VL 2014 -- VL Verilog Toolkit, 2014 Edition
# Copyright (C) 2008-2015 Centaur Technology
#
# Contact:
#   Centaur Technology Formal Verification Group
#   7600-C N. Capital of Texas Highway, Suite 300, Austin, TX 78731, USA.
#   http://www.centtech.com/
#
# License: (An MIT/X11-style license)
#
#   Permission is hereby granted, free of charge, to any person obtaining a
#   copy of this software and associated documentation files (the "Software"),
#   to deal in the Software without restriction, including without limitation
#   the rights to use, copy, modify, merge, publish, distribute, sublicense,
#   and/or sell copies of the Software, and to permit persons to whom the
#   Software is furnished to do so, subject to the following conditions:
#
#   The above copyright notice and this permission notice shall be included in
#   all copies or substantial portions of the Software.
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#   IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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# Original author: Jared Davis <jared@centtech.com>

require_relative '../utils'

outlaw_bad_warnings()
outlaw_warning_global("VL-PROGRAMMING-ERROR")

match_warning(:m0, "VL-LUCID-UNUSED", "height");

match_warning(:m1, "VL-WARN-TRUNCATION", "a & b");

match_warning(:m2, "VL-LUCID-UNUSED", "alpha")
match_warning(:m2, "VL-LUCID-UNUSED", "beta")
match_warning(:m2, "VL-LUCID-UNSET", "omega")

match_warning(:m3, "VL-LUCID-UNUSED", "alpha")
match_warning(:m3, "VL-LUCID-UNUSED", "beta")
match_warning(:m3, "VL-LUCID-UNSET", "omega")

test_passed()



