read_verilog ../common/tribuf.v
hierarchy -top tristate
proc
tribuf
flatten
synth
equiv_opt -assert -map +/xilinx/cells_sim.v -map +/simcells.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd tristate # Constrain all select calls below inside the top module
select -assert-count 2 t:IBUF
select -assert-count 1 t:INV
select -assert-count 1 t:OBUFT
select -assert-none t:IBUF t:INV t:OBUFT %% t:* %D
