read_verilog ../common/add_sub.v
hierarchy -top top
proc
equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 10 t:EFX_ADD
select -assert-count 4  t:EFX_LUT4
select -assert-none t:EFX_ADD t:EFX_LUT4 %% t:* %D

