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	title={Example-driven interconnect synthesis for heterogeneous coarse-grain reconfigurable logic},
	author={C. Wolf and Johann Glaser and Florian Schupfer and Jan Haase and Christoph Grimm},
	booktitle={FDL Proceeding of the 2012 Forum on Specification and Design Languages},
	pages={194--201},
	year={2012}
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@incollection{intersynthFdlBookChapter,
	title={Methodology and Example-Driven Interconnect Synthesis for Designing Heterogeneous Coarse-Grain Reconfigurable Architectures},
	author={Johann Glaser and C. Wolf},
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	editor={Jan Haase},
	publisher={Springer},
	year={2013},
	note={to appear}
}

@unpublished{BACC,
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@MISC{Odin,
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@inproceedings{vtr2012,
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@MISC{LogicSynthesis,
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@ARTICLE{Verilog2005, 
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@ARTICLE{VerilogSynth, 
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@ARTICLE{VHDL,
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@ARTICLE{VHDLSynth,
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@ARTICLE{IP-XACT, 
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@INPROCEEDINGS{fsmextract, 
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	keywords={circuit CAD;finite state machines;microcontrollers;FSM;control-intensive circuits;finite state machines;flattened gate-level netlist;state register elimination technique;Automata;Circuit synthesis;Continuous wavelet transforms;Design automation;Digital circuits;Hardware design languages;Logic;Microcontrollers;Registers;Signal processing}, 
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@inproceedings{VIS,
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