read_verilog ../common/add_sub.v
hierarchy -top top
proc
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-min 11 t:LUT4
select -assert-count 2 t:PFUMX
select -assert-none t:LUT4 t:PFUMX %% t:* %D

