read_verilog -icells <<EOT

module top(input C, D, E, S, R, output [11:0] Q);

$_DFF_P_ ff0 (.C(C), .D(D), .Q(Q[0]));
$_DFF_PP0_ ff1 (.C(C), .D(D), .R(R), .Q(Q[1]));
$_DFF_PP1_ ff2 (.C(C), .D(D), .R(R), .Q(Q[2]));
$_DFFSR_PPP_ ff3 (.C(C), .D(D), .R(R), .S(S), .Q(Q[3]));
$_DFFSR_NNN_ ff4 (.C(C), .D(D), .R(R), .S(S), .Q(Q[4]));
$_DFFE_PP_ ff5 (.C(C), .D(D), .E(E), .Q(Q[5]));

assign Q[11:6] = ~Q[5:0];

endmodule

EOT

simplemap

design -save orig
read_liberty -lib dfflibmap.lib

equiv_opt -map dfflibmap-sim.v -assert -multiclock dfflibmap -liberty dfflibmap.lib
equiv_opt -map dfflibmap-sim.v -assert -multiclock dfflibmap -prepare -liberty dfflibmap.lib

dfflibmap -prepare -liberty dffl*bmap.lib
equiv_opt -map dfflibmap-sim.v -assert -multiclock dfflibmap -map-only -liberty dfflibmap.lib

design -load orig
dfflibmap -liberty dfflibmap.lib
clean

select -assert-count 5 t:$_NOT_
select -assert-count 1 t:dffn
select -assert-count 4 t:dffsr
select -assert-count 1 t:dffe
select -assert-none t:dffn t:dffsr t:dffe t:$_NOT_ %% %n t:* %i

design -load orig
dfflibmap -prepare -liberty dfflibmap.lib

select -assert-count 11 t:$_NOT_
select -assert-count 1 t:$_DFF_N_
select -assert-count 4 t:$_DFFSR_PPP_
select -assert-count 1 t:$_DFFE_NP_
select -assert-none t:$_DFF_N_ t:$_DFFSR_PPP_ t:$_DFFE_NP_ t:$_NOT_ %% %n t:* %i

design -load orig
dfflibmap -map-only -liberty dfflibmap.lib

select -assert-count 6 t:$_NOT_
select -assert-count 0 t:dffn
select -assert-count 1 t:dffsr

design -load orig
dfflibmap -prepare -liberty dfflibmap.lib
dfflibmap -map-only -liberty dfflibmap.lib
clean

select -assert-count 5 t:$_NOT_
select -assert-count 1 t:dffn
select -assert-count 4 t:dffsr
select -assert-count 1 t:dffe
select -assert-none t:dffn t:dffsr t:dffe t:$_NOT_ %% %n t:* %i

design -load orig
dfflibmap -prepare -liberty dfflibmap_dffn_dffe.lib -liberty dfflibmap_dffsr.lib
dfflibmap -map-only -liberty dfflibmap_dffn_dffe.lib -liberty dfflibmap_dffsr.lib
clean

select -assert-count 5 t:$_NOT_
select -assert-count 1 t:dffn
select -assert-count 1 t:dffe
select -assert-count 4 t:dffsr
select -assert-none t:dffn t:dffsr t:dffe t:$_NOT_ %% %n t:* %i

design -load orig
dfflibmap -liberty dfflibmap.lib -dont_use *ffn
clean

select -assert-count 0 t:dffn
select -assert-count 5 t:dffsr
select -assert-count 1 t:dffe

design -load orig
dfflibmap -liberty dfflibmap.lib -liberty dfflibmap_dffsr_mixedpol.lib -dont_use dffsr
clean
# We have one more _NOT_ than with the regular dffsr
select -assert-count 6 t:$_NOT_
select -assert-count 1 t:dffn
select -assert-count 4 t:dffsr_mixedpol
select -assert-count 1 t:dffe
# The additional NOT is on ff2.
# Originally, ff2.R is an active high "set".
# dffsr_mixedpol has functionally swapped labels due to the next_state inversion,
# so we use its CLEAR port for the "set",
# but we have to invert it because the CLEAR pin is active low.
# ff2.CLEAR = !R
select -assert-count 1 c:ff2 %x:+[CLEAR] %ci t:$_NOT_ %i
