-- This module is generated by vhdl_pkg.xsl
--   (2016-2020, hackfin@section5.ch)
--
--   Changes may be void.
--


library ieee;
	use ieee.std_logic_1164.all;
	use ieee.numeric_std.all;


package components is

component CCU2C is
  generic (
    INJECT1_0 : string := "YES";
    INJECT1_1 : string := "YES";
    INIT0 : std_logic_vector := "0000000000000000";
    INIT1 : std_logic_vector := "0000000000000000"  );
  port (
    A0 :   in  std_ulogic;
    A1 :   in  std_ulogic;
    B0 :   in  std_ulogic;
    B1 :   in  std_ulogic;
    C0 :   in  std_ulogic;
    C1 :   in  std_ulogic;
    D0 :   in  std_ulogic;
    D1 :   in  std_ulogic;
    CIN :   in  std_ulogic;
    S0 :   out  std_ulogic;
    S1 :   out  std_ulogic;
    COUT :   out  std_ulogic  );
end component;

component AND2 is
  port (
    A :   in  std_logic;
    B :   in  std_logic;
    Z :   out  std_logic  );
end component;

component AND3 is
  port (
    A :   in  std_logic;
    B :   in  std_logic;
    C :   in  std_logic;
    Z :   out  std_logic  );
end component;

component AND4 is
  port (
    A :   in  std_logic;
    B :   in  std_logic;
    C :   in  std_logic;
    D :   in  std_logic;
    Z :   out  std_logic  );
end component;

component AND5 is
  port (
    A :   in  std_logic;
    B :   in  std_logic;
    C :   in  std_logic;
    D :   in  std_logic;
    E :   in  std_logic;
    Z :   out  std_logic  );
end component;

component FD1P3AX is
  generic (
    GSR : string := "ENABLED"  );
  port (
    D :   in  std_logic;
    SP :   in  std_logic;
    CK :   in  std_logic;
    Q :   out  std_logic  );
end component;

component FD1P3AY is
  generic (
    GSR : string := "ENABLED"  );
  port (
    D :   in  std_logic;
    SP :   in  std_logic;
    CK :   in  std_logic;
    Q :   out  std_logic  );
end component;

component FD1P3BX is
  generic (
    GSR : string := "ENABLED"  );
  port (
    D :   in  std_logic;
    SP :   in  std_logic;
    CK :   in  std_logic;
    PD :   in  std_logic;
    Q :   out  std_logic  );
end component;

component FD1P3DX is
  generic (
    GSR : string := "ENABLED"  );
  port (
    D :   in  std_logic;
    SP :   in  std_logic;
    CK :   in  std_logic;
    CD :   in  std_logic;
    Q :   out  std_logic  );
end component;

component FD1P3IX is
  generic (
    GSR : string := "ENABLED"  );
  port (
    D :   in  std_logic;
    SP :   in  std_logic;
    CK :   in  std_logic;
    CD :   in  std_logic;
    Q :   out  std_logic  );
end component;

component FD1P3JX is
  generic (
    GSR : string := "ENABLED"  );
  port (
    D :   in  std_logic;
    SP :   in  std_logic;
    CK :   in  std_logic;
    PD :   in  std_logic;
    Q :   out  std_logic  );
end component;

component FD1S3AX is
  generic (
    GSR : string := "ENABLED"  );
  port (
    D :   in  std_logic;
    CK :   in  std_logic;
    Q :   out  std_logic  );
end component;

component FD1S3AY is
  generic (
    GSR : string := "ENABLED"  );
  port (
    D :   in  std_logic;
    CK :   in  std_logic;
    Q :   out  std_logic  );
end component;

component FD1S3BX is
  generic (
    GSR : string := "ENABLED"  );
  port (
    D :   in  std_logic;
    CK :   in  std_logic;
    PD :   in  std_logic;
    Q :   out  std_logic  );
end component;

component FD1S3DX is
  generic (
    GSR : string := "ENABLED"  );
  port (
    D :   in  std_logic;
    CK :   in  std_logic;
    CD :   in  std_logic;
    Q :   out  std_logic  );
end component;

component FD1S3IX is
  generic (
    GSR : string := "ENABLED"  );
  port (
    D :   in  std_logic;
    CK :   in  std_logic;
    CD :   in  std_logic;
    Q :   out  std_logic  );
end component;

component FD1S3JX is
  generic (
    GSR : string := "ENABLED"  );
  port (
    D :   in  std_logic;
    CK :   in  std_logic;
    PD :   in  std_logic;
    Q :   out  std_logic  );
end component;

component FL1P3AZ is
  generic (
    GSR : string := "ENABLED"  );
  port (
    D0 :   in  std_logic;
    D1 :   in  std_logic;
    SP :   in  std_logic;
    CK :   in  std_logic;
    SD :   in  std_logic;
    Q :   out  std_logic  );
end component;

component FL1P3AY is
  generic (
    GSR : string := "ENABLED"  );
  port (
    D0 :   in  std_logic;
    D1 :   in  std_logic;
    SP :   in  std_logic;
    CK :   in  std_logic;
    SD :   in  std_logic;
    Q :   out  std_logic  );
end component;

component FL1P3BX is
  generic (
    GSR : string := "ENABLED"  );
  port (
    D0 :   in  std_logic;
    D1 :   in  std_logic;
    SP :   in  std_logic;
    CK :   in  std_logic;
    SD :   in  std_logic;
    PD :   in  std_logic;
    Q :   out  std_logic  );
end component;

component FL1P3DX is
  generic (
    GSR : string := "ENABLED"  );
  port (
    D0 :   in  std_logic;
    D1 :   in  std_logic;
    SP :   in  std_logic;
    CK :   in  std_logic;
    SD :   in  std_logic;
    CD :   in  std_logic;
    Q :   out  std_logic  );
end component;

component FL1P3IY is
  generic (
    GSR : string := "ENABLED"  );
  port (
    D0 :   in  std_logic;
    D1 :   in  std_logic;
    SP :   in  std_logic;
    CK :   in  std_logic;
    SD :   in  std_logic;
    CD :   in  std_logic;
    Q :   out  std_logic  );
end component;

component FL1P3JY is
  generic (
    GSR : string := "ENABLED"  );
  port (
    D0 :   in  std_logic;
    D1 :   in  std_logic;
    SP :   in  std_logic;
    CK :   in  std_logic;
    SD :   in  std_logic;
    PD :   in  std_logic;
    Q :   out  std_logic  );
end component;

component FL1S3AX is
  generic (
    GSR : string := "ENABLED"  );
  port (
    D0 :   in  std_logic;
    D1 :   in  std_logic;
    CK :   in  std_logic;
    SD :   in  std_logic;
    Q :   out  std_logic  );
end component;

component FL1S3AY is
  generic (
    GSR : string := "ENABLED"  );
  port (
    D0 :   in  std_logic;
    D1 :   in  std_logic;
    CK :   in  std_logic;
    SD :   in  std_logic;
    Q :   out  std_logic  );
end component;

component GSR is
  port (
    GSR :   in  std_logic  );
end component;

component SGSR is
  port (
    GSR :   in  std_logic;
    CLK :   in  std_logic  );
end component;

component INV is
  port (
    A :   in  std_logic;
    Z :   out  std_logic  );
end component;

component IFS1P3BX is
  generic (
    GSR : string := "ENABLED"  );
  port (
    D :   in  std_logic;
    SP :   in  std_logic;
    SCLK :   in  std_logic;
    PD :   in  std_logic;
    Q :   out  std_logic  );
end component;

component IFS1P3DX is
  generic (
    GSR : string := "ENABLED"  );
  port (
    D :   in  std_logic;
    SP :   in  std_logic;
    SCLK :   in  std_logic;
    CD :   in  std_logic;
    Q :   out  std_logic  );
end component;

component IFS1P3IX is
  generic (
    GSR : string := "ENABLED"  );
  port (
    D :   in  std_logic;
    SP :   in  std_logic;
    SCLK :   in  std_logic;
    CD :   in  std_logic;
    Q :   out  std_logic  );
end component;

component IFS1P3JX is
  generic (
    GSR : string := "ENABLED"  );
  port (
    D :   in  std_logic;
    SP :   in  std_logic;
    SCLK :   in  std_logic;
    PD :   in  std_logic;
    Q :   out  std_logic  );
end component;

component IFS1S1B is
  generic (
    GSR : string := "ENABLED"  );
  port (
    D :   in  std_logic;
    SCLK :   in  std_logic;
    PD :   in  std_logic;
    Q :   out  std_logic  );
end component;

component IFS1S1D is
  generic (
    GSR : string := "ENABLED"  );
  port (
    D :   in  std_logic;
    SCLK :   in  std_logic;
    CD :   in  std_logic;
    Q :   out  std_logic  );
end component;

component IFS1S1I is
  generic (
    GSR : string := "ENABLED"  );
  port (
    D :   in  std_logic;
    SCLK :   in  std_logic;
    CD :   in  std_logic;
    Q :   out  std_logic  );
end component;

component IFS1S1J is
  generic (
    GSR : string := "ENABLED"  );
  port (
    D :   in  std_logic;
    SCLK :   in  std_logic;
    PD :   in  std_logic;
    Q :   out  std_logic  );
end component;

component L6MUX21 is
  port (
    D0 :   in  std_logic;
    D1 :   in  std_logic;
    SD :   in  std_logic;
    Z :   out  std_logic  );
end component;

component MUX21 is
  port (
    D0 :   in  std_logic;
    D1 :   in  std_logic;
    SD :   in  std_logic;
    Z :   out  std_logic  );
end component;

component MUX41 is
  port (
    D0 :   in  std_logic;
    D1 :   in  std_logic;
    D2 :   in  std_logic;
    D3 :   in  std_logic;
    SD1 :   in  std_logic;
    SD2 :   in  std_logic;
    Z :   out  std_logic  );
end component;

component MUX81 is
  port (
    D0 :   in  std_logic;
    D1 :   in  std_logic;
    D2 :   in  std_logic;
    D3 :   in  std_logic;
    D4 :   in  std_logic;
    D5 :   in  std_logic;
    D6 :   in  std_logic;
    D7 :   in  std_logic;
    SD1 :   in  std_logic;
    SD2 :   in  std_logic;
    SD3 :   in  std_logic;
    Z :   out  std_logic  );
end component;

component MUX161 is
  port (
    D0 :   in  std_logic;
    D1 :   in  std_logic;
    D2 :   in  std_logic;
    D3 :   in  std_logic;
    D4 :   in  std_logic;
    D5 :   in  std_logic;
    D6 :   in  std_logic;
    D7 :   in  std_logic;
    D8 :   in  std_logic;
    D9 :   in  std_logic;
    D10 :   in  std_logic;
    D11 :   in  std_logic;
    D12 :   in  std_logic;
    D13 :   in  std_logic;
    D14 :   in  std_logic;
    D15 :   in  std_logic;
    SD1 :   in  std_logic;
    SD2 :   in  std_logic;
    SD3 :   in  std_logic;
    SD4 :   in  std_logic;
    Z :   out  std_logic  );
end component;

component MUX321 is
  port (
    D0 :   in  std_logic;
    D1 :   in  std_logic;
    D2 :   in  std_logic;
    D3 :   in  std_logic;
    D4 :   in  std_logic;
    D5 :   in  std_logic;
    D6 :   in  std_logic;
    D7 :   in  std_logic;
    D8 :   in  std_logic;
    D9 :   in  std_logic;
    D10 :   in  std_logic;
    D11 :   in  std_logic;
    D12 :   in  std_logic;
    D13 :   in  std_logic;
    D14 :   in  std_logic;
    D15 :   in  std_logic;
    D16 :   in  std_logic;
    D17 :   in  std_logic;
    D18 :   in  std_logic;
    D19 :   in  std_logic;
    D20 :   in  std_logic;
    D21 :   in  std_logic;
    D22 :   in  std_logic;
    D23 :   in  std_logic;
    D24 :   in  std_logic;
    D25 :   in  std_logic;
    D26 :   in  std_logic;
    D27 :   in  std_logic;
    D28 :   in  std_logic;
    D29 :   in  std_logic;
    D30 :   in  std_logic;
    D31 :   in  std_logic;
    SD1 :   in  std_logic;
    SD2 :   in  std_logic;
    SD3 :   in  std_logic;
    SD4 :   in  std_logic;
    SD5 :   in  std_logic;
    Z :   out  std_logic  );
end component;

component ND2 is
  port (
    A :   in  std_logic;
    B :   in  std_logic;
    Z :   out  std_logic  );
end component;

component ND3 is
  port (
    A :   in  std_logic;
    B :   in  std_logic;
    C :   in  std_logic;
    Z :   out  std_logic  );
end component;

component ND4 is
  port (
    A :   in  std_logic;
    B :   in  std_logic;
    C :   in  std_logic;
    D :   in  std_logic;
    Z :   out  std_logic  );
end component;

component ND5 is
  port (
    A :   in  std_logic;
    B :   in  std_logic;
    C :   in  std_logic;
    D :   in  std_logic;
    E :   in  std_logic;
    Z :   out  std_logic  );
end component;

component NR2 is
  port (
    A :   in  std_logic;
    B :   in  std_logic;
    Z :   out  std_logic  );
end component;

component NR3 is
  port (
    A :   in  std_logic;
    B :   in  std_logic;
    C :   in  std_logic;
    Z :   out  std_logic  );
end component;

component NR4 is
  port (
    A :   in  std_logic;
    B :   in  std_logic;
    C :   in  std_logic;
    D :   in  std_logic;
    Z :   out  std_logic  );
end component;

component NR5 is
  port (
    A :   in  std_logic;
    B :   in  std_logic;
    C :   in  std_logic;
    D :   in  std_logic;
    E :   in  std_logic;
    Z :   out  std_logic  );
end component;

component OFS1P3BX is
  generic (
    GSR : string := "ENABLED"  );
  port (
    D :   in  std_logic;
    SP :   in  std_logic;
    SCLK :   in  std_logic;
    PD :   in  std_logic;
    Q :   out  std_logic  );
end component;

component OFS1P3DX is
  generic (
    GSR : string := "ENABLED"  );
  port (
    D :   in  std_logic;
    SP :   in  std_logic;
    SCLK :   in  std_logic;
    CD :   in  std_logic;
    Q :   out  std_logic  );
end component;

component OFS1P3IX is
  generic (
    GSR : string := "ENABLED"  );
  port (
    D :   in  std_logic;
    SP :   in  std_logic;
    SCLK :   in  std_logic;
    CD :   in  std_logic;
    Q :   out  std_logic  );
end component;

component OFS1P3JX is
  generic (
    GSR : string := "ENABLED"  );
  port (
    D :   in  std_logic;
    SP :   in  std_logic;
    SCLK :   in  std_logic;
    PD :   in  std_logic;
    Q :   out  std_logic  );
end component;

component OR2 is
  port (
    A :   in  std_logic;
    B :   in  std_logic;
    Z :   out  std_logic  );
end component;

component OR3 is
  port (
    A :   in  std_logic;
    B :   in  std_logic;
    C :   in  std_logic;
    Z :   out  std_logic  );
end component;

component OR4 is
  port (
    A :   in  std_logic;
    B :   in  std_logic;
    C :   in  std_logic;
    D :   in  std_logic;
    Z :   out  std_logic  );
end component;

component OR5 is
  port (
    A :   in  std_logic;
    B :   in  std_logic;
    C :   in  std_logic;
    D :   in  std_logic;
    E :   in  std_logic;
    Z :   out  std_logic  );
end component;

component PFUMX is
  port (
    ALUT :   in  std_logic;
    BLUT :   in  std_logic;
    C0 :   in  std_logic;
    Z :   out  std_logic  );
end component;

component ROM16X1A is
  generic (
    INITVAL : std_logic_vector := "0000000000000000"  );
  port (
    AD0 :   in  std_logic;
    AD1 :   in  std_logic;
    AD2 :   in  std_logic;
    AD3 :   in  std_logic;
    DO0 :   out  std_logic  );
end component;

component ROM32X1A is
  generic (
    INITVAL : std_logic_vector := "00000000000000000000000000000000"  );
  port (
    AD0 :   in  std_logic;
    AD1 :   in  std_logic;
    AD2 :   in  std_logic;
    AD3 :   in  std_logic;
    AD4 :   in  std_logic;
    DO0 :   out  std_logic  );
end component;

component ROM64X1A is
  generic (
    INITVAL : std_logic_vector := "0000000000000000000000000000000000000000000000000000000000000000"  );
  port (
    AD0 :   in  std_logic;
    AD1 :   in  std_logic;
    AD2 :   in  std_logic;
    AD3 :   in  std_logic;
    AD4 :   in  std_logic;
    AD5 :   in  std_logic;
    DO0 :   out  std_logic  );
end component;

component ROM128X1A is
  generic (
    INITVAL : std_logic_vector := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"  );
  port (
    AD0 :   in  std_logic;
    AD1 :   in  std_logic;
    AD2 :   in  std_logic;
    AD3 :   in  std_logic;
    AD4 :   in  std_logic;
    AD5 :   in  std_logic;
    AD6 :   in  std_logic;
    DO0 :   out  std_logic  );
end component;

component ROM256X1A is
  generic (
    INITVAL : std_logic_vector := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"  );
  port (
    AD0 :   in  std_logic;
    AD1 :   in  std_logic;
    AD2 :   in  std_logic;
    AD3 :   in  std_logic;
    AD4 :   in  std_logic;
    AD5 :   in  std_logic;
    AD6 :   in  std_logic;
    AD7 :   in  std_logic;
    DO0 :   out  std_logic  );
end component;

component VHI is
  port (
    Z :   out  std_logic  );
end component;

component VLO is
  port (
    Z :   out  std_logic  );
end component;

component XOR2 is
  port (
    A :   in  std_logic;
    B :   in  std_logic;
    Z :   out  std_logic  );
end component;

component XOR3 is
  port (
    A :   in  std_logic;
    B :   in  std_logic;
    C :   in  std_logic;
    Z :   out  std_logic  );
end component;

component XOR4 is
  port (
    A :   in  std_logic;
    B :   in  std_logic;
    C :   in  std_logic;
    D :   in  std_logic;
    Z :   out  std_logic  );
end component;

component XOR5 is
  port (
    A :   in  std_logic;
    B :   in  std_logic;
    C :   in  std_logic;
    D :   in  std_logic;
    E :   in  std_logic;
    Z :   out  std_logic  );
end component;

component XOR11 is
  port (
    A :   in  std_logic;
    B :   in  std_logic;
    C :   in  std_logic;
    D :   in  std_logic;
    E :   in  std_logic;
    F :   in  std_logic;
    G :   in  std_logic;
    H :   in  std_logic;
    I :   in  std_logic;
    J :   in  std_logic;
    K :   in  std_logic;
    Z :   out  std_logic  );
end component;

component XOR21 is
  port (
    A :   in  std_logic;
    B :   in  std_logic;
    C :   in  std_logic;
    D :   in  std_logic;
    E :   in  std_logic;
    F :   in  std_logic;
    G :   in  std_logic;
    H :   in  std_logic;
    I :   in  std_logic;
    J :   in  std_logic;
    K :   in  std_logic;
    L :   in  std_logic;
    M :   in  std_logic;
    N :   in  std_logic;
    O :   in  std_logic;
    P :   in  std_logic;
    Q :   in  std_logic;
    R :   in  std_logic;
    S :   in  std_logic;
    T :   in  std_logic;
    U :   in  std_logic;
    Z :   out  std_logic  );
end component;

component XNOR2 is
  port (
    A :   in  std_logic;
    B :   in  std_logic;
    Z :   out  std_logic  );
end component;

component XNOR3 is
  port (
    A :   in  std_logic;
    B :   in  std_logic;
    C :   in  std_logic;
    Z :   out  std_logic  );
end component;

component XNOR4 is
  port (
    A :   in  std_logic;
    B :   in  std_logic;
    C :   in  std_logic;
    D :   in  std_logic;
    Z :   out  std_logic  );
end component;

component XNOR5 is
  port (
    A :   in  std_logic;
    B :   in  std_logic;
    C :   in  std_logic;
    D :   in  std_logic;
    E :   in  std_logic;
    Z :   out  std_logic  );
end component;

component ILVDS is
  port (
    A :   in  std_logic;
    AN :   in  std_logic;
    Z :   out  std_logic  );
end component;

component OLVDS is
  port (
    A :   in  std_logic;
    Z :   out  std_logic;
    ZN :   out  std_logic  );
end component;

component BB is
  port (
    B :   inout  std_logic;
    I :   in  std_logic;
    T :   in  std_logic;
    O :   out  std_logic  );
end component;

component BBPD is
  port (
    B :   inout  std_logic;
    I :   in  std_logic;
    T :   in  std_logic;
    O :   out  std_logic  );
end component;

component BBPU is
  port (
    B :   inout  std_logic;
    I :   in  std_logic;
    T :   in  std_logic;
    O :   out  std_logic  );
end component;

component IB is
  port (
    I :   in  std_logic;
    O :   out  std_logic  );
end component;

component IBPD is
  port (
    I :   in  std_logic;
    O :   out  std_logic  );
end component;

component IBPU is
  port (
    I :   in  std_logic;
    O :   out  std_logic  );
end component;

component OB is
  port (
    I :   in  std_logic;
    O :   out  std_logic  );
end component;

component OBCO is
  port (
    I :   in  std_logic;
    OT :   out  std_logic;
    OC :   out  std_logic  );
end component;

component OBZ is
  port (
    I :   in  std_logic;
    T :   in  std_logic;
    O :   out  std_logic  );
end component;

component OBZPU is
  port (
    I :   in  std_logic;
    T :   in  std_logic;
    O :   out  std_logic  );
end component;

component LUT4 is
  generic (
    INIT : std_logic_vector := ""  );
  port (
    A :   in  std_ulogic;
    B :   in  std_ulogic;
    C :   in  std_ulogic;
    D :   in  std_ulogic;
    Z :   out  std_ulogic  );
end component;

component LUT5 is
  generic (
    INIT : std_logic_vector := ""  );
  port (
    A :   in  std_ulogic;
    B :   in  std_ulogic;
    C :   in  std_ulogic;
    D :   in  std_ulogic;
    E :   in  std_ulogic;
    Z :   out  std_ulogic  );
end component;

component LUT6 is
  generic (
    INIT : std_logic_vector := ""  );
  port (
    A :   in  std_ulogic;
    B :   in  std_ulogic;
    C :   in  std_ulogic;
    D :   in  std_ulogic;
    E :   in  std_ulogic;
    F :   in  std_ulogic;
    Z :   out  std_ulogic  );
end component;

component LUT7 is
  generic (
    INIT : std_logic_vector := ""  );
  port (
    A :   in  std_ulogic;
    B :   in  std_ulogic;
    C :   in  std_ulogic;
    D :   in  std_ulogic;
    E :   in  std_ulogic;
    F :   in  std_ulogic;
    G :   in  std_ulogic;
    Z :   out  std_ulogic  );
end component;

component LUT8 is
  generic (
    INIT : std_logic_vector := ""  );
  port (
    A :   in  std_ulogic;
    B :   in  std_ulogic;
    C :   in  std_ulogic;
    D :   in  std_ulogic;
    E :   in  std_ulogic;
    F :   in  std_ulogic;
    G :   in  std_ulogic;
    H :   in  std_ulogic;
    Z :   out  std_ulogic  );
end component;

component MULT9X9C is
  generic (
    REG_INPUTA_CLK : string := "NONE";
    REG_INPUTA_CE : string := "CE0";
    REG_INPUTA_RST : string := "RST0";
    REG_INPUTB_CLK : string := "NONE";
    REG_INPUTB_CE : string := "CE0";
    REG_INPUTB_RST : string := "RST0";
    REG_PIPELINE_CLK : string := "NONE";
    REG_PIPELINE_CE : string := "CE0";
    REG_PIPELINE_RST : string := "RST0";
    REG_OUTPUT_CLK : string := "NONE";
    REG_OUTPUT_CE : string := "CE0";
    REG_OUTPUT_RST : string := "RST0";
    GSR : string := "ENABLED";
    CAS_MATCH_REG : string := "FALSE";
    MULT_BYPASS : string := "DISABLED";
    RESETMODE : string := "SYNC"  );
  port (
    A8 :   in  std_logic;
    A7 :   in  std_logic;
    A6 :   in  std_logic;
    A5 :   in  std_logic;
    A4 :   in  std_logic;
    A3 :   in  std_logic;
    A2 :   in  std_logic;
    A1 :   in  std_logic;
    A0 :   in  std_logic;
    B8 :   in  std_logic;
    B7 :   in  std_logic;
    B6 :   in  std_logic;
    B5 :   in  std_logic;
    B4 :   in  std_logic;
    B3 :   in  std_logic;
    B2 :   in  std_logic;
    B1 :   in  std_logic;
    B0 :   in  std_logic;
    SIGNEDA :   in  std_logic;
    SIGNEDB :   in  std_logic;
    SOURCEA :   in  std_logic;
    SOURCEB :   in  std_logic;
    CLK3 :   in  std_logic;
    CLK2 :   in  std_logic;
    CLK1 :   in  std_logic;
    CLK0 :   in  std_logic;
    CE3 :   in  std_logic;
    CE2 :   in  std_logic;
    CE1 :   in  std_logic;
    CE0 :   in  std_logic;
    RST3 :   in  std_logic;
    RST2 :   in  std_logic;
    RST1 :   in  std_logic;
    RST0 :   in  std_logic;
    SRIA8 :   in  std_logic;
    SRIA7 :   in  std_logic;
    SRIA6 :   in  std_logic;
    SRIA5 :   in  std_logic;
    SRIA4 :   in  std_logic;
    SRIA3 :   in  std_logic;
    SRIA2 :   in  std_logic;
    SRIA1 :   in  std_logic;
    SRIA0 :   in  std_logic;
    SRIB8 :   in  std_logic;
    SRIB7 :   in  std_logic;
    SRIB6 :   in  std_logic;
    SRIB5 :   in  std_logic;
    SRIB4 :   in  std_logic;
    SRIB3 :   in  std_logic;
    SRIB2 :   in  std_logic;
    SRIB1 :   in  std_logic;
    SRIB0 :   in  std_logic;
    SROA8 :   out  std_logic;
    SROA7 :   out  std_logic;
    SROA6 :   out  std_logic;
    SROA5 :   out  std_logic;
    SROA4 :   out  std_logic;
    SROA3 :   out  std_logic;
    SROA2 :   out  std_logic;
    SROA1 :   out  std_logic;
    SROA0 :   out  std_logic;
    SROB8 :   out  std_logic;
    SROB7 :   out  std_logic;
    SROB6 :   out  std_logic;
    SROB5 :   out  std_logic;
    SROB4 :   out  std_logic;
    SROB3 :   out  std_logic;
    SROB2 :   out  std_logic;
    SROB1 :   out  std_logic;
    SROB0 :   out  std_logic;
    ROA8 :   out  std_logic;
    ROA7 :   out  std_logic;
    ROA6 :   out  std_logic;
    ROA5 :   out  std_logic;
    ROA4 :   out  std_logic;
    ROA3 :   out  std_logic;
    ROA2 :   out  std_logic;
    ROA1 :   out  std_logic;
    ROA0 :   out  std_logic;
    ROB8 :   out  std_logic;
    ROB7 :   out  std_logic;
    ROB6 :   out  std_logic;
    ROB5 :   out  std_logic;
    ROB4 :   out  std_logic;
    ROB3 :   out  std_logic;
    ROB2 :   out  std_logic;
    ROB1 :   out  std_logic;
    ROB0 :   out  std_logic;
    P17 :   out  std_logic;
    P16 :   out  std_logic;
    P15 :   out  std_logic;
    P14 :   out  std_logic;
    P13 :   out  std_logic;
    P12 :   out  std_logic;
    P11 :   out  std_logic;
    P10 :   out  std_logic;
    P9 :   out  std_logic;
    P8 :   out  std_logic;
    P7 :   out  std_logic;
    P6 :   out  std_logic;
    P5 :   out  std_logic;
    P4 :   out  std_logic;
    P3 :   out  std_logic;
    P2 :   out  std_logic;
    P1 :   out  std_logic;
    P0 :   out  std_logic;
    SIGNEDP :   out  std_logic  );
end component;

component MULT9X9D is
  generic (
    REG_INPUTA_CLK : string := "NONE";
    REG_INPUTA_CE : string := "CE0";
    REG_INPUTA_RST : string := "RST0";
    REG_INPUTB_CLK : string := "NONE";
    REG_INPUTB_CE : string := "CE0";
    REG_INPUTB_RST : string := "RST0";
    REG_INPUTC_CLK : string := "NONE";
    REG_INPUTC_CE : string := "CE0";
    REG_INPUTC_RST : string := "RST0";
    REG_PIPELINE_CLK : string := "NONE";
    REG_PIPELINE_CE : string := "CE0";
    REG_PIPELINE_RST : string := "RST0";
    REG_OUTPUT_CLK : string := "NONE";
    REG_OUTPUT_CE : string := "CE0";
    REG_OUTPUT_RST : string := "RST0";
    CLK0_DIV : string := "ENABLED";
    CLK1_DIV : string := "ENABLED";
    CLK2_DIV : string := "ENABLED";
    CLK3_DIV : string := "ENABLED";
    HIGHSPEED_CLK : string := "NONE";
    GSR : string := "ENABLED";
    CAS_MATCH_REG : string := "FALSE";
    SOURCEB_MODE : string := "B_SHIFT";
    MULT_BYPASS : string := "DISABLED";
    RESETMODE : string := "SYNC"  );
  port (
    A8 :   in  std_logic;
    A7 :   in  std_logic;
    A6 :   in  std_logic;
    A5 :   in  std_logic;
    A4 :   in  std_logic;
    A3 :   in  std_logic;
    A2 :   in  std_logic;
    A1 :   in  std_logic;
    A0 :   in  std_logic;
    B8 :   in  std_logic;
    B7 :   in  std_logic;
    B6 :   in  std_logic;
    B5 :   in  std_logic;
    B4 :   in  std_logic;
    B3 :   in  std_logic;
    B2 :   in  std_logic;
    B1 :   in  std_logic;
    B0 :   in  std_logic;
    C8 :   in  std_logic;
    C7 :   in  std_logic;
    C6 :   in  std_logic;
    C5 :   in  std_logic;
    C4 :   in  std_logic;
    C3 :   in  std_logic;
    C2 :   in  std_logic;
    C1 :   in  std_logic;
    C0 :   in  std_logic;
    SIGNEDA :   in  std_logic;
    SIGNEDB :   in  std_logic;
    SOURCEA :   in  std_logic;
    SOURCEB :   in  std_logic;
    CLK3 :   in  std_logic;
    CLK2 :   in  std_logic;
    CLK1 :   in  std_logic;
    CLK0 :   in  std_logic;
    CE3 :   in  std_logic;
    CE2 :   in  std_logic;
    CE1 :   in  std_logic;
    CE0 :   in  std_logic;
    RST3 :   in  std_logic;
    RST2 :   in  std_logic;
    RST1 :   in  std_logic;
    RST0 :   in  std_logic;
    SRIA8 :   in  std_logic;
    SRIA7 :   in  std_logic;
    SRIA6 :   in  std_logic;
    SRIA5 :   in  std_logic;
    SRIA4 :   in  std_logic;
    SRIA3 :   in  std_logic;
    SRIA2 :   in  std_logic;
    SRIA1 :   in  std_logic;
    SRIA0 :   in  std_logic;
    SRIB8 :   in  std_logic;
    SRIB7 :   in  std_logic;
    SRIB6 :   in  std_logic;
    SRIB5 :   in  std_logic;
    SRIB4 :   in  std_logic;
    SRIB3 :   in  std_logic;
    SRIB2 :   in  std_logic;
    SRIB1 :   in  std_logic;
    SRIB0 :   in  std_logic;
    SROA8 :   out  std_logic;
    SROA7 :   out  std_logic;
    SROA6 :   out  std_logic;
    SROA5 :   out  std_logic;
    SROA4 :   out  std_logic;
    SROA3 :   out  std_logic;
    SROA2 :   out  std_logic;
    SROA1 :   out  std_logic;
    SROA0 :   out  std_logic;
    SROB8 :   out  std_logic;
    SROB7 :   out  std_logic;
    SROB6 :   out  std_logic;
    SROB5 :   out  std_logic;
    SROB4 :   out  std_logic;
    SROB3 :   out  std_logic;
    SROB2 :   out  std_logic;
    SROB1 :   out  std_logic;
    SROB0 :   out  std_logic;
    ROA8 :   out  std_logic;
    ROA7 :   out  std_logic;
    ROA6 :   out  std_logic;
    ROA5 :   out  std_logic;
    ROA4 :   out  std_logic;
    ROA3 :   out  std_logic;
    ROA2 :   out  std_logic;
    ROA1 :   out  std_logic;
    ROA0 :   out  std_logic;
    ROB8 :   out  std_logic;
    ROB7 :   out  std_logic;
    ROB6 :   out  std_logic;
    ROB5 :   out  std_logic;
    ROB4 :   out  std_logic;
    ROB3 :   out  std_logic;
    ROB2 :   out  std_logic;
    ROB1 :   out  std_logic;
    ROB0 :   out  std_logic;
    ROC8 :   out  std_logic;
    ROC7 :   out  std_logic;
    ROC6 :   out  std_logic;
    ROC5 :   out  std_logic;
    ROC4 :   out  std_logic;
    ROC3 :   out  std_logic;
    ROC2 :   out  std_logic;
    ROC1 :   out  std_logic;
    ROC0 :   out  std_logic;
    P17 :   out  std_logic;
    P16 :   out  std_logic;
    P15 :   out  std_logic;
    P14 :   out  std_logic;
    P13 :   out  std_logic;
    P12 :   out  std_logic;
    P11 :   out  std_logic;
    P10 :   out  std_logic;
    P9 :   out  std_logic;
    P8 :   out  std_logic;
    P7 :   out  std_logic;
    P6 :   out  std_logic;
    P5 :   out  std_logic;
    P4 :   out  std_logic;
    P3 :   out  std_logic;
    P2 :   out  std_logic;
    P1 :   out  std_logic;
    P0 :   out  std_logic;
    SIGNEDP :   out  std_logic  );
end component;

component MULT18X18C is
  generic (
    REG_INPUTA_CLK : string := "NONE";
    REG_INPUTA_CE : string := "CE0";
    REG_INPUTA_RST : string := "RST0";
    REG_INPUTB_CLK : string := "NONE";
    REG_INPUTB_CE : string := "CE0";
    REG_INPUTB_RST : string := "RST0";
    REG_PIPELINE_CLK : string := "NONE";
    REG_PIPELINE_CE : string := "CE0";
    REG_PIPELINE_RST : string := "RST0";
    REG_OUTPUT_CLK : string := "NONE";
    REG_OUTPUT_CE : string := "CE0";
    REG_OUTPUT_RST : string := "RST0";
    CAS_MATCH_REG : string := "FALSE";
    MULT_BYPASS : string := "DISABLED";
    GSR : string := "ENABLED";
    RESETMODE : string := "SYNC"  );
  port (
    A17 :   in  std_logic;
    A16 :   in  std_logic;
    A15 :   in  std_logic;
    A14 :   in  std_logic;
    A13 :   in  std_logic;
    A12 :   in  std_logic;
    A11 :   in  std_logic;
    A10 :   in  std_logic;
    A9 :   in  std_logic;
    A8 :   in  std_logic;
    A7 :   in  std_logic;
    A6 :   in  std_logic;
    A5 :   in  std_logic;
    A4 :   in  std_logic;
    A3 :   in  std_logic;
    A2 :   in  std_logic;
    A1 :   in  std_logic;
    A0 :   in  std_logic;
    B17 :   in  std_logic;
    B16 :   in  std_logic;
    B15 :   in  std_logic;
    B14 :   in  std_logic;
    B13 :   in  std_logic;
    B12 :   in  std_logic;
    B11 :   in  std_logic;
    B10 :   in  std_logic;
    B9 :   in  std_logic;
    B8 :   in  std_logic;
    B7 :   in  std_logic;
    B6 :   in  std_logic;
    B5 :   in  std_logic;
    B4 :   in  std_logic;
    B3 :   in  std_logic;
    B2 :   in  std_logic;
    B1 :   in  std_logic;
    B0 :   in  std_logic;
    SIGNEDA :   in  std_logic;
    SIGNEDB :   in  std_logic;
    SOURCEA :   in  std_logic;
    SOURCEB :   in  std_logic;
    CLK3 :   in  std_logic;
    CLK2 :   in  std_logic;
    CLK1 :   in  std_logic;
    CLK0 :   in  std_logic;
    CE3 :   in  std_logic;
    CE2 :   in  std_logic;
    CE1 :   in  std_logic;
    CE0 :   in  std_logic;
    RST3 :   in  std_logic;
    RST2 :   in  std_logic;
    RST1 :   in  std_logic;
    RST0 :   in  std_logic;
    SRIA17 :   in  std_logic;
    SRIA16 :   in  std_logic;
    SRIA15 :   in  std_logic;
    SRIA14 :   in  std_logic;
    SRIA13 :   in  std_logic;
    SRIA12 :   in  std_logic;
    SRIA11 :   in  std_logic;
    SRIA10 :   in  std_logic;
    SRIA9 :   in  std_logic;
    SRIA8 :   in  std_logic;
    SRIA7 :   in  std_logic;
    SRIA6 :   in  std_logic;
    SRIA5 :   in  std_logic;
    SRIA4 :   in  std_logic;
    SRIA3 :   in  std_logic;
    SRIA2 :   in  std_logic;
    SRIA1 :   in  std_logic;
    SRIA0 :   in  std_logic;
    SRIB17 :   in  std_logic;
    SRIB16 :   in  std_logic;
    SRIB15 :   in  std_logic;
    SRIB14 :   in  std_logic;
    SRIB13 :   in  std_logic;
    SRIB12 :   in  std_logic;
    SRIB11 :   in  std_logic;
    SRIB10 :   in  std_logic;
    SRIB9 :   in  std_logic;
    SRIB8 :   in  std_logic;
    SRIB7 :   in  std_logic;
    SRIB6 :   in  std_logic;
    SRIB5 :   in  std_logic;
    SRIB4 :   in  std_logic;
    SRIB3 :   in  std_logic;
    SRIB2 :   in  std_logic;
    SRIB1 :   in  std_logic;
    SRIB0 :   in  std_logic;
    SROA17 :   out  std_logic;
    SROA16 :   out  std_logic;
    SROA15 :   out  std_logic;
    SROA14 :   out  std_logic;
    SROA13 :   out  std_logic;
    SROA12 :   out  std_logic;
    SROA11 :   out  std_logic;
    SROA10 :   out  std_logic;
    SROA9 :   out  std_logic;
    SROA8 :   out  std_logic;
    SROA7 :   out  std_logic;
    SROA6 :   out  std_logic;
    SROA5 :   out  std_logic;
    SROA4 :   out  std_logic;
    SROA3 :   out  std_logic;
    SROA2 :   out  std_logic;
    SROA1 :   out  std_logic;
    SROA0 :   out  std_logic;
    SROB17 :   out  std_logic;
    SROB16 :   out  std_logic;
    SROB15 :   out  std_logic;
    SROB14 :   out  std_logic;
    SROB13 :   out  std_logic;
    SROB12 :   out  std_logic;
    SROB11 :   out  std_logic;
    SROB10 :   out  std_logic;
    SROB9 :   out  std_logic;
    SROB8 :   out  std_logic;
    SROB7 :   out  std_logic;
    SROB6 :   out  std_logic;
    SROB5 :   out  std_logic;
    SROB4 :   out  std_logic;
    SROB3 :   out  std_logic;
    SROB2 :   out  std_logic;
    SROB1 :   out  std_logic;
    SROB0 :   out  std_logic;
    ROA17 :   out  std_logic;
    ROA16 :   out  std_logic;
    ROA15 :   out  std_logic;
    ROA14 :   out  std_logic;
    ROA13 :   out  std_logic;
    ROA12 :   out  std_logic;
    ROA11 :   out  std_logic;
    ROA10 :   out  std_logic;
    ROA9 :   out  std_logic;
    ROA8 :   out  std_logic;
    ROA7 :   out  std_logic;
    ROA6 :   out  std_logic;
    ROA5 :   out  std_logic;
    ROA4 :   out  std_logic;
    ROA3 :   out  std_logic;
    ROA2 :   out  std_logic;
    ROA1 :   out  std_logic;
    ROA0 :   out  std_logic;
    ROB17 :   out  std_logic;
    ROB16 :   out  std_logic;
    ROB15 :   out  std_logic;
    ROB14 :   out  std_logic;
    ROB13 :   out  std_logic;
    ROB12 :   out  std_logic;
    ROB11 :   out  std_logic;
    ROB10 :   out  std_logic;
    ROB9 :   out  std_logic;
    ROB8 :   out  std_logic;
    ROB7 :   out  std_logic;
    ROB6 :   out  std_logic;
    ROB5 :   out  std_logic;
    ROB4 :   out  std_logic;
    ROB3 :   out  std_logic;
    ROB2 :   out  std_logic;
    ROB1 :   out  std_logic;
    ROB0 :   out  std_logic;
    P35 :   out  std_logic;
    P34 :   out  std_logic;
    P33 :   out  std_logic;
    P32 :   out  std_logic;
    P31 :   out  std_logic;
    P30 :   out  std_logic;
    P29 :   out  std_logic;
    P28 :   out  std_logic;
    P27 :   out  std_logic;
    P26 :   out  std_logic;
    P25 :   out  std_logic;
    P24 :   out  std_logic;
    P23 :   out  std_logic;
    P22 :   out  std_logic;
    P21 :   out  std_logic;
    P20 :   out  std_logic;
    P19 :   out  std_logic;
    P18 :   out  std_logic;
    P17 :   out  std_logic;
    P16 :   out  std_logic;
    P15 :   out  std_logic;
    P14 :   out  std_logic;
    P13 :   out  std_logic;
    P12 :   out  std_logic;
    P11 :   out  std_logic;
    P10 :   out  std_logic;
    P9 :   out  std_logic;
    P8 :   out  std_logic;
    P7 :   out  std_logic;
    P6 :   out  std_logic;
    P5 :   out  std_logic;
    P4 :   out  std_logic;
    P3 :   out  std_logic;
    P2 :   out  std_logic;
    P1 :   out  std_logic;
    P0 :   out  std_logic;
    SIGNEDP :   out  std_logic  );
end component;

component MULT18X18D is
  generic (
    REG_INPUTA_CLK : string := "NONE";
    REG_INPUTA_CE : string := "CE0";
    REG_INPUTA_RST : string := "RST0";
    REG_INPUTB_CLK : string := "NONE";
    REG_INPUTB_CE : string := "CE0";
    REG_INPUTB_RST : string := "RST0";
    REG_INPUTC_CLK : string := "NONE";
    REG_INPUTC_CE : string := "CE0";
    REG_INPUTC_RST : string := "RST0";
    REG_PIPELINE_CLK : string := "NONE";
    REG_PIPELINE_CE : string := "CE0";
    REG_PIPELINE_RST : string := "RST0";
    REG_OUTPUT_CLK : string := "NONE";
    REG_OUTPUT_CE : string := "CE0";
    REG_OUTPUT_RST : string := "RST0";
    CLK0_DIV : string := "ENABLED";
    CLK1_DIV : string := "ENABLED";
    CLK2_DIV : string := "ENABLED";
    CLK3_DIV : string := "ENABLED";
    HIGHSPEED_CLK : string := "NONE";
    GSR : string := "ENABLED";
    CAS_MATCH_REG : string := "FALSE";
    SOURCEB_MODE : string := "B_SHIFT";
    MULT_BYPASS : string := "DISABLED";
    RESETMODE : string := "SYNC"  );
  port (
    A17 :   in  std_logic;
    A16 :   in  std_logic;
    A15 :   in  std_logic;
    A14 :   in  std_logic;
    A13 :   in  std_logic;
    A12 :   in  std_logic;
    A11 :   in  std_logic;
    A10 :   in  std_logic;
    A9 :   in  std_logic;
    A8 :   in  std_logic;
    A7 :   in  std_logic;
    A6 :   in  std_logic;
    A5 :   in  std_logic;
    A4 :   in  std_logic;
    A3 :   in  std_logic;
    A2 :   in  std_logic;
    A1 :   in  std_logic;
    A0 :   in  std_logic;
    B17 :   in  std_logic;
    B16 :   in  std_logic;
    B15 :   in  std_logic;
    B14 :   in  std_logic;
    B13 :   in  std_logic;
    B12 :   in  std_logic;
    B11 :   in  std_logic;
    B10 :   in  std_logic;
    B9 :   in  std_logic;
    B8 :   in  std_logic;
    B7 :   in  std_logic;
    B6 :   in  std_logic;
    B5 :   in  std_logic;
    B4 :   in  std_logic;
    B3 :   in  std_logic;
    B2 :   in  std_logic;
    B1 :   in  std_logic;
    B0 :   in  std_logic;
    C17 :   in  std_logic;
    C16 :   in  std_logic;
    C15 :   in  std_logic;
    C14 :   in  std_logic;
    C13 :   in  std_logic;
    C12 :   in  std_logic;
    C11 :   in  std_logic;
    C10 :   in  std_logic;
    C9 :   in  std_logic;
    C8 :   in  std_logic;
    C7 :   in  std_logic;
    C6 :   in  std_logic;
    C5 :   in  std_logic;
    C4 :   in  std_logic;
    C3 :   in  std_logic;
    C2 :   in  std_logic;
    C1 :   in  std_logic;
    C0 :   in  std_logic;
    SIGNEDA :   in  std_logic;
    SIGNEDB :   in  std_logic;
    SOURCEA :   in  std_logic;
    SOURCEB :   in  std_logic;
    CLK3 :   in  std_logic;
    CLK2 :   in  std_logic;
    CLK1 :   in  std_logic;
    CLK0 :   in  std_logic;
    CE3 :   in  std_logic;
    CE2 :   in  std_logic;
    CE1 :   in  std_logic;
    CE0 :   in  std_logic;
    RST3 :   in  std_logic;
    RST2 :   in  std_logic;
    RST1 :   in  std_logic;
    RST0 :   in  std_logic;
    SRIA17 :   in  std_logic;
    SRIA16 :   in  std_logic;
    SRIA15 :   in  std_logic;
    SRIA14 :   in  std_logic;
    SRIA13 :   in  std_logic;
    SRIA12 :   in  std_logic;
    SRIA11 :   in  std_logic;
    SRIA10 :   in  std_logic;
    SRIA9 :   in  std_logic;
    SRIA8 :   in  std_logic;
    SRIA7 :   in  std_logic;
    SRIA6 :   in  std_logic;
    SRIA5 :   in  std_logic;
    SRIA4 :   in  std_logic;
    SRIA3 :   in  std_logic;
    SRIA2 :   in  std_logic;
    SRIA1 :   in  std_logic;
    SRIA0 :   in  std_logic;
    SRIB17 :   in  std_logic;
    SRIB16 :   in  std_logic;
    SRIB15 :   in  std_logic;
    SRIB14 :   in  std_logic;
    SRIB13 :   in  std_logic;
    SRIB12 :   in  std_logic;
    SRIB11 :   in  std_logic;
    SRIB10 :   in  std_logic;
    SRIB9 :   in  std_logic;
    SRIB8 :   in  std_logic;
    SRIB7 :   in  std_logic;
    SRIB6 :   in  std_logic;
    SRIB5 :   in  std_logic;
    SRIB4 :   in  std_logic;
    SRIB3 :   in  std_logic;
    SRIB2 :   in  std_logic;
    SRIB1 :   in  std_logic;
    SRIB0 :   in  std_logic;
    SROA17 :   out  std_logic;
    SROA16 :   out  std_logic;
    SROA15 :   out  std_logic;
    SROA14 :   out  std_logic;
    SROA13 :   out  std_logic;
    SROA12 :   out  std_logic;
    SROA11 :   out  std_logic;
    SROA10 :   out  std_logic;
    SROA9 :   out  std_logic;
    SROA8 :   out  std_logic;
    SROA7 :   out  std_logic;
    SROA6 :   out  std_logic;
    SROA5 :   out  std_logic;
    SROA4 :   out  std_logic;
    SROA3 :   out  std_logic;
    SROA2 :   out  std_logic;
    SROA1 :   out  std_logic;
    SROA0 :   out  std_logic;
    SROB17 :   out  std_logic;
    SROB16 :   out  std_logic;
    SROB15 :   out  std_logic;
    SROB14 :   out  std_logic;
    SROB13 :   out  std_logic;
    SROB12 :   out  std_logic;
    SROB11 :   out  std_logic;
    SROB10 :   out  std_logic;
    SROB9 :   out  std_logic;
    SROB8 :   out  std_logic;
    SROB7 :   out  std_logic;
    SROB6 :   out  std_logic;
    SROB5 :   out  std_logic;
    SROB4 :   out  std_logic;
    SROB3 :   out  std_logic;
    SROB2 :   out  std_logic;
    SROB1 :   out  std_logic;
    SROB0 :   out  std_logic;
    ROA17 :   out  std_logic;
    ROA16 :   out  std_logic;
    ROA15 :   out  std_logic;
    ROA14 :   out  std_logic;
    ROA13 :   out  std_logic;
    ROA12 :   out  std_logic;
    ROA11 :   out  std_logic;
    ROA10 :   out  std_logic;
    ROA9 :   out  std_logic;
    ROA8 :   out  std_logic;
    ROA7 :   out  std_logic;
    ROA6 :   out  std_logic;
    ROA5 :   out  std_logic;
    ROA4 :   out  std_logic;
    ROA3 :   out  std_logic;
    ROA2 :   out  std_logic;
    ROA1 :   out  std_logic;
    ROA0 :   out  std_logic;
    ROB17 :   out  std_logic;
    ROB16 :   out  std_logic;
    ROB15 :   out  std_logic;
    ROB14 :   out  std_logic;
    ROB13 :   out  std_logic;
    ROB12 :   out  std_logic;
    ROB11 :   out  std_logic;
    ROB10 :   out  std_logic;
    ROB9 :   out  std_logic;
    ROB8 :   out  std_logic;
    ROB7 :   out  std_logic;
    ROB6 :   out  std_logic;
    ROB5 :   out  std_logic;
    ROB4 :   out  std_logic;
    ROB3 :   out  std_logic;
    ROB2 :   out  std_logic;
    ROB1 :   out  std_logic;
    ROB0 :   out  std_logic;
    ROC17 :   out  std_logic;
    ROC16 :   out  std_logic;
    ROC15 :   out  std_logic;
    ROC14 :   out  std_logic;
    ROC13 :   out  std_logic;
    ROC12 :   out  std_logic;
    ROC11 :   out  std_logic;
    ROC10 :   out  std_logic;
    ROC9 :   out  std_logic;
    ROC8 :   out  std_logic;
    ROC7 :   out  std_logic;
    ROC6 :   out  std_logic;
    ROC5 :   out  std_logic;
    ROC4 :   out  std_logic;
    ROC3 :   out  std_logic;
    ROC2 :   out  std_logic;
    ROC1 :   out  std_logic;
    ROC0 :   out  std_logic;
    P35 :   out  std_logic;
    P34 :   out  std_logic;
    P33 :   out  std_logic;
    P32 :   out  std_logic;
    P31 :   out  std_logic;
    P30 :   out  std_logic;
    P29 :   out  std_logic;
    P28 :   out  std_logic;
    P27 :   out  std_logic;
    P26 :   out  std_logic;
    P25 :   out  std_logic;
    P24 :   out  std_logic;
    P23 :   out  std_logic;
    P22 :   out  std_logic;
    P21 :   out  std_logic;
    P20 :   out  std_logic;
    P19 :   out  std_logic;
    P18 :   out  std_logic;
    P17 :   out  std_logic;
    P16 :   out  std_logic;
    P15 :   out  std_logic;
    P14 :   out  std_logic;
    P13 :   out  std_logic;
    P12 :   out  std_logic;
    P11 :   out  std_logic;
    P10 :   out  std_logic;
    P9 :   out  std_logic;
    P8 :   out  std_logic;
    P7 :   out  std_logic;
    P6 :   out  std_logic;
    P5 :   out  std_logic;
    P4 :   out  std_logic;
    P3 :   out  std_logic;
    P2 :   out  std_logic;
    P1 :   out  std_logic;
    P0 :   out  std_logic;
    SIGNEDP :   out  std_logic  );
end component;

component ALU24A is
  generic (
    REG_OUTPUT_CLK : string := "NONE";
    REG_OUTPUT_CE : string := "CE0";
    REG_OUTPUT_RST : string := "RST0";
    REG_OPCODE_0_CLK : string := "NONE";
    REG_OPCODE_0_CE : string := "CE0";
    REG_OPCODE_0_RST : string := "RST0";
    REG_OPCODE_1_CLK : string := "NONE";
    REG_OPCODE_1_CE : string := "CE0";
    REG_OPCODE_1_RST : string := "RST0";
    GSR : string := "ENABLED";
    RESETMODE : string := "SYNC"  );
  port (
    CE3 :   in  std_logic;
    CE2 :   in  std_logic;
    CE1 :   in  std_logic;
    CE0 :   in  std_logic;
    CLK3 :   in  std_logic;
    CLK2 :   in  std_logic;
    CLK1 :   in  std_logic;
    CLK0 :   in  std_logic;
    RST3 :   in  std_logic;
    RST2 :   in  std_logic;
    RST1 :   in  std_logic;
    RST0 :   in  std_logic;
    SIGNEDIA :   in  std_logic;
    SIGNEDIB :   in  std_logic;
    MA17 :   in  std_logic;
    MA16 :   in  std_logic;
    MA15 :   in  std_logic;
    MA14 :   in  std_logic;
    MA13 :   in  std_logic;
    MA12 :   in  std_logic;
    MA11 :   in  std_logic;
    MA10 :   in  std_logic;
    MA9 :   in  std_logic;
    MA8 :   in  std_logic;
    MA7 :   in  std_logic;
    MA6 :   in  std_logic;
    MA5 :   in  std_logic;
    MA4 :   in  std_logic;
    MA3 :   in  std_logic;
    MA2 :   in  std_logic;
    MA1 :   in  std_logic;
    MA0 :   in  std_logic;
    MB17 :   in  std_logic;
    MB16 :   in  std_logic;
    MB15 :   in  std_logic;
    MB14 :   in  std_logic;
    MB13 :   in  std_logic;
    MB12 :   in  std_logic;
    MB11 :   in  std_logic;
    MB10 :   in  std_logic;
    MB9 :   in  std_logic;
    MB8 :   in  std_logic;
    MB7 :   in  std_logic;
    MB6 :   in  std_logic;
    MB5 :   in  std_logic;
    MB4 :   in  std_logic;
    MB3 :   in  std_logic;
    MB2 :   in  std_logic;
    MB1 :   in  std_logic;
    MB0 :   in  std_logic;
    CIN23 :   in  std_logic;
    CIN22 :   in  std_logic;
    CIN21 :   in  std_logic;
    CIN20 :   in  std_logic;
    CIN19 :   in  std_logic;
    CIN18 :   in  std_logic;
    CIN17 :   in  std_logic;
    CIN16 :   in  std_logic;
    CIN15 :   in  std_logic;
    CIN14 :   in  std_logic;
    CIN13 :   in  std_logic;
    CIN12 :   in  std_logic;
    CIN11 :   in  std_logic;
    CIN10 :   in  std_logic;
    CIN9 :   in  std_logic;
    CIN8 :   in  std_logic;
    CIN7 :   in  std_logic;
    CIN6 :   in  std_logic;
    CIN5 :   in  std_logic;
    CIN4 :   in  std_logic;
    CIN3 :   in  std_logic;
    CIN2 :   in  std_logic;
    CIN1 :   in  std_logic;
    CIN0 :   in  std_logic;
    OPADDNSUB :   in  std_logic;
    OPCINSEL :   in  std_logic;
    R23 :   out  std_logic;
    R22 :   out  std_logic;
    R21 :   out  std_logic;
    R20 :   out  std_logic;
    R19 :   out  std_logic;
    R18 :   out  std_logic;
    R17 :   out  std_logic;
    R16 :   out  std_logic;
    R15 :   out  std_logic;
    R14 :   out  std_logic;
    R13 :   out  std_logic;
    R12 :   out  std_logic;
    R11 :   out  std_logic;
    R10 :   out  std_logic;
    R9 :   out  std_logic;
    R8 :   out  std_logic;
    R7 :   out  std_logic;
    R6 :   out  std_logic;
    R5 :   out  std_logic;
    R4 :   out  std_logic;
    R3 :   out  std_logic;
    R2 :   out  std_logic;
    R1 :   out  std_logic;
    R0 :   out  std_logic  );
end component;

component ALU54A is
  generic (
    REG_INPUTC0_CLK : string := "NONE";
    REG_INPUTC0_CE : string := "CE0";
    REG_INPUTC0_RST : string := "RST0";
    REG_INPUTC1_CLK : string := "NONE";
    REG_INPUTC1_CE : string := "CE0";
    REG_INPUTC1_RST : string := "RST0";
    REG_OPCODEOP0_0_CLK : string := "NONE";
    REG_OPCODEOP0_0_CE : string := "CE0";
    REG_OPCODEOP0_0_RST : string := "RST0";
    REG_OPCODEOP1_0_CLK : string := "NONE";
    REG_OPCODEOP0_1_CLK : string := "NONE";
    REG_OPCODEOP0_1_CE : string := "CE0";
    REG_OPCODEOP0_1_RST : string := "RST0";
    REG_OPCODEOP1_1_CLK : string := "NONE";
    REG_OPCODEIN_0_CLK : string := "NONE";
    REG_OPCODEIN_0_CE : string := "CE0";
    REG_OPCODEIN_0_RST : string := "RST0";
    REG_OPCODEIN_1_CLK : string := "NONE";
    REG_OPCODEIN_1_CE : string := "CE0";
    REG_OPCODEIN_1_RST : string := "RST0";
    REG_OUTPUT0_CLK : string := "NONE";
    REG_OUTPUT0_CE : string := "CE0";
    REG_OUTPUT0_RST : string := "RST0";
    REG_OUTPUT1_CLK : string := "NONE";
    REG_OUTPUT1_CE : string := "CE0";
    REG_OUTPUT1_RST : string := "RST0";
    REG_FLAG_CLK : string := "NONE";
    REG_FLAG_CE : string := "CE0";
    REG_FLAG_RST : string := "RST0";
    MCPAT_SOURCE : string := "STATIC";
    MASKPAT_SOURCE : string := "STATIC";
    MASK01 : string := "0x00000000000000";
    MCPAT : string := "0x00000000000000";
    MASKPAT : string := "0x00000000000000";
    RNDPAT : string := "0x00000000000000";
    GSR : string := "ENABLED";
    RESETMODE : string := "SYNC";
    MULT9_MODE : string := "DISABLED";
    LEGACY : string := "DISABLED"  );
  port (
    CE3 :   in  std_logic;
    CE2 :   in  std_logic;
    CE1 :   in  std_logic;
    CE0 :   in  std_logic;
    CLK3 :   in  std_logic;
    CLK2 :   in  std_logic;
    CLK1 :   in  std_logic;
    CLK0 :   in  std_logic;
    RST3 :   in  std_logic;
    RST2 :   in  std_logic;
    RST1 :   in  std_logic;
    RST0 :   in  std_logic;
    SIGNEDIA :   in  std_logic;
    SIGNEDIB :   in  std_logic;
    SIGNEDCIN :   in  std_logic;
    A35 :   in  std_logic;
    A34 :   in  std_logic;
    A33 :   in  std_logic;
    A32 :   in  std_logic;
    A31 :   in  std_logic;
    A30 :   in  std_logic;
    A29 :   in  std_logic;
    A28 :   in  std_logic;
    A27 :   in  std_logic;
    A26 :   in  std_logic;
    A25 :   in  std_logic;
    A24 :   in  std_logic;
    A23 :   in  std_logic;
    A22 :   in  std_logic;
    A21 :   in  std_logic;
    A20 :   in  std_logic;
    A19 :   in  std_logic;
    A18 :   in  std_logic;
    A17 :   in  std_logic;
    A16 :   in  std_logic;
    A15 :   in  std_logic;
    A14 :   in  std_logic;
    A13 :   in  std_logic;
    A12 :   in  std_logic;
    A11 :   in  std_logic;
    A10 :   in  std_logic;
    A9 :   in  std_logic;
    A8 :   in  std_logic;
    A7 :   in  std_logic;
    A6 :   in  std_logic;
    A5 :   in  std_logic;
    A4 :   in  std_logic;
    A3 :   in  std_logic;
    A2 :   in  std_logic;
    A1 :   in  std_logic;
    A0 :   in  std_logic;
    B35 :   in  std_logic;
    B34 :   in  std_logic;
    B33 :   in  std_logic;
    B32 :   in  std_logic;
    B31 :   in  std_logic;
    B30 :   in  std_logic;
    B29 :   in  std_logic;
    B28 :   in  std_logic;
    B27 :   in  std_logic;
    B26 :   in  std_logic;
    B25 :   in  std_logic;
    B24 :   in  std_logic;
    B23 :   in  std_logic;
    B22 :   in  std_logic;
    B21 :   in  std_logic;
    B20 :   in  std_logic;
    B19 :   in  std_logic;
    B18 :   in  std_logic;
    B17 :   in  std_logic;
    B16 :   in  std_logic;
    B15 :   in  std_logic;
    B14 :   in  std_logic;
    B13 :   in  std_logic;
    B12 :   in  std_logic;
    B11 :   in  std_logic;
    B10 :   in  std_logic;
    B9 :   in  std_logic;
    B8 :   in  std_logic;
    B7 :   in  std_logic;
    B6 :   in  std_logic;
    B5 :   in  std_logic;
    B4 :   in  std_logic;
    B3 :   in  std_logic;
    B2 :   in  std_logic;
    B1 :   in  std_logic;
    B0 :   in  std_logic;
    C53 :   in  std_logic;
    C52 :   in  std_logic;
    C51 :   in  std_logic;
    C50 :   in  std_logic;
    C49 :   in  std_logic;
    C48 :   in  std_logic;
    C47 :   in  std_logic;
    C46 :   in  std_logic;
    C45 :   in  std_logic;
    C44 :   in  std_logic;
    C43 :   in  std_logic;
    C42 :   in  std_logic;
    C41 :   in  std_logic;
    C40 :   in  std_logic;
    C39 :   in  std_logic;
    C38 :   in  std_logic;
    C37 :   in  std_logic;
    C36 :   in  std_logic;
    C35 :   in  std_logic;
    C34 :   in  std_logic;
    C33 :   in  std_logic;
    C32 :   in  std_logic;
    C31 :   in  std_logic;
    C30 :   in  std_logic;
    C29 :   in  std_logic;
    C28 :   in  std_logic;
    C27 :   in  std_logic;
    C26 :   in  std_logic;
    C25 :   in  std_logic;
    C24 :   in  std_logic;
    C23 :   in  std_logic;
    C22 :   in  std_logic;
    C21 :   in  std_logic;
    C20 :   in  std_logic;
    C19 :   in  std_logic;
    C18 :   in  std_logic;
    C17 :   in  std_logic;
    C16 :   in  std_logic;
    C15 :   in  std_logic;
    C14 :   in  std_logic;
    C13 :   in  std_logic;
    C12 :   in  std_logic;
    C11 :   in  std_logic;
    C10 :   in  std_logic;
    C9 :   in  std_logic;
    C8 :   in  std_logic;
    C7 :   in  std_logic;
    C6 :   in  std_logic;
    C5 :   in  std_logic;
    C4 :   in  std_logic;
    C3 :   in  std_logic;
    C2 :   in  std_logic;
    C1 :   in  std_logic;
    C0 :   in  std_logic;
    MA35 :   in  std_logic;
    MA34 :   in  std_logic;
    MA33 :   in  std_logic;
    MA32 :   in  std_logic;
    MA31 :   in  std_logic;
    MA30 :   in  std_logic;
    MA29 :   in  std_logic;
    MA28 :   in  std_logic;
    MA27 :   in  std_logic;
    MA26 :   in  std_logic;
    MA25 :   in  std_logic;
    MA24 :   in  std_logic;
    MA23 :   in  std_logic;
    MA22 :   in  std_logic;
    MA21 :   in  std_logic;
    MA20 :   in  std_logic;
    MA19 :   in  std_logic;
    MA18 :   in  std_logic;
    MA17 :   in  std_logic;
    MA16 :   in  std_logic;
    MA15 :   in  std_logic;
    MA14 :   in  std_logic;
    MA13 :   in  std_logic;
    MA12 :   in  std_logic;
    MA11 :   in  std_logic;
    MA10 :   in  std_logic;
    MA9 :   in  std_logic;
    MA8 :   in  std_logic;
    MA7 :   in  std_logic;
    MA6 :   in  std_logic;
    MA5 :   in  std_logic;
    MA4 :   in  std_logic;
    MA3 :   in  std_logic;
    MA2 :   in  std_logic;
    MA1 :   in  std_logic;
    MA0 :   in  std_logic;
    MB35 :   in  std_logic;
    MB34 :   in  std_logic;
    MB33 :   in  std_logic;
    MB32 :   in  std_logic;
    MB31 :   in  std_logic;
    MB30 :   in  std_logic;
    MB29 :   in  std_logic;
    MB28 :   in  std_logic;
    MB27 :   in  std_logic;
    MB26 :   in  std_logic;
    MB25 :   in  std_logic;
    MB24 :   in  std_logic;
    MB23 :   in  std_logic;
    MB22 :   in  std_logic;
    MB21 :   in  std_logic;
    MB20 :   in  std_logic;
    MB19 :   in  std_logic;
    MB18 :   in  std_logic;
    MB17 :   in  std_logic;
    MB16 :   in  std_logic;
    MB15 :   in  std_logic;
    MB14 :   in  std_logic;
    MB13 :   in  std_logic;
    MB12 :   in  std_logic;
    MB11 :   in  std_logic;
    MB10 :   in  std_logic;
    MB9 :   in  std_logic;
    MB8 :   in  std_logic;
    MB7 :   in  std_logic;
    MB6 :   in  std_logic;
    MB5 :   in  std_logic;
    MB4 :   in  std_logic;
    MB3 :   in  std_logic;
    MB2 :   in  std_logic;
    MB1 :   in  std_logic;
    MB0 :   in  std_logic;
    CIN53 :   in  std_logic;
    CIN52 :   in  std_logic;
    CIN51 :   in  std_logic;
    CIN50 :   in  std_logic;
    CIN49 :   in  std_logic;
    CIN48 :   in  std_logic;
    CIN47 :   in  std_logic;
    CIN46 :   in  std_logic;
    CIN45 :   in  std_logic;
    CIN44 :   in  std_logic;
    CIN43 :   in  std_logic;
    CIN42 :   in  std_logic;
    CIN41 :   in  std_logic;
    CIN40 :   in  std_logic;
    CIN39 :   in  std_logic;
    CIN38 :   in  std_logic;
    CIN37 :   in  std_logic;
    CIN36 :   in  std_logic;
    CIN35 :   in  std_logic;
    CIN34 :   in  std_logic;
    CIN33 :   in  std_logic;
    CIN32 :   in  std_logic;
    CIN31 :   in  std_logic;
    CIN30 :   in  std_logic;
    CIN29 :   in  std_logic;
    CIN28 :   in  std_logic;
    CIN27 :   in  std_logic;
    CIN26 :   in  std_logic;
    CIN25 :   in  std_logic;
    CIN24 :   in  std_logic;
    CIN23 :   in  std_logic;
    CIN22 :   in  std_logic;
    CIN21 :   in  std_logic;
    CIN20 :   in  std_logic;
    CIN19 :   in  std_logic;
    CIN18 :   in  std_logic;
    CIN17 :   in  std_logic;
    CIN16 :   in  std_logic;
    CIN15 :   in  std_logic;
    CIN14 :   in  std_logic;
    CIN13 :   in  std_logic;
    CIN12 :   in  std_logic;
    CIN11 :   in  std_logic;
    CIN10 :   in  std_logic;
    CIN9 :   in  std_logic;
    CIN8 :   in  std_logic;
    CIN7 :   in  std_logic;
    CIN6 :   in  std_logic;
    CIN5 :   in  std_logic;
    CIN4 :   in  std_logic;
    CIN3 :   in  std_logic;
    CIN2 :   in  std_logic;
    CIN1 :   in  std_logic;
    CIN0 :   in  std_logic;
    OP10 :   in  std_logic;
    OP9 :   in  std_logic;
    OP8 :   in  std_logic;
    OP7 :   in  std_logic;
    OP6 :   in  std_logic;
    OP5 :   in  std_logic;
    OP4 :   in  std_logic;
    OP3 :   in  std_logic;
    OP2 :   in  std_logic;
    OP1 :   in  std_logic;
    OP0 :   in  std_logic;
    R53 :   out  std_logic;
    R52 :   out  std_logic;
    R51 :   out  std_logic;
    R50 :   out  std_logic;
    R49 :   out  std_logic;
    R48 :   out  std_logic;
    R47 :   out  std_logic;
    R46 :   out  std_logic;
    R45 :   out  std_logic;
    R44 :   out  std_logic;
    R43 :   out  std_logic;
    R42 :   out  std_logic;
    R41 :   out  std_logic;
    R40 :   out  std_logic;
    R39 :   out  std_logic;
    R38 :   out  std_logic;
    R37 :   out  std_logic;
    R36 :   out  std_logic;
    R35 :   out  std_logic;
    R34 :   out  std_logic;
    R33 :   out  std_logic;
    R32 :   out  std_logic;
    R31 :   out  std_logic;
    R30 :   out  std_logic;
    R29 :   out  std_logic;
    R28 :   out  std_logic;
    R27 :   out  std_logic;
    R26 :   out  std_logic;
    R25 :   out  std_logic;
    R24 :   out  std_logic;
    R23 :   out  std_logic;
    R22 :   out  std_logic;
    R21 :   out  std_logic;
    R20 :   out  std_logic;
    R19 :   out  std_logic;
    R18 :   out  std_logic;
    R17 :   out  std_logic;
    R16 :   out  std_logic;
    R15 :   out  std_logic;
    R14 :   out  std_logic;
    R13 :   out  std_logic;
    R12 :   out  std_logic;
    R11 :   out  std_logic;
    R10 :   out  std_logic;
    R9 :   out  std_logic;
    R8 :   out  std_logic;
    R7 :   out  std_logic;
    R6 :   out  std_logic;
    R5 :   out  std_logic;
    R4 :   out  std_logic;
    R3 :   out  std_logic;
    R2 :   out  std_logic;
    R1 :   out  std_logic;
    R0 :   out  std_logic;
    EQZ :   out  std_logic;
    EQZM :   out  std_logic;
    EQOM :   out  std_logic;
    EQPAT :   out  std_logic;
    EQPATB :   out  std_logic;
    OVER :   out  std_logic;
    UNDER :   out  std_logic;
    OVERUNDER :   out  std_logic;
    SIGNEDR :   out  std_logic  );
end component;

component ALU24B is
  generic (
    REG_OUTPUT_CLK : string := "NONE";
    REG_OUTPUT_CE : string := "CE0";
    REG_OUTPUT_RST : string := "RST0";
    REG_OPCODE_0_CLK : string := "NONE";
    REG_OPCODE_0_CE : string := "CE0";
    REG_OPCODE_0_RST : string := "RST0";
    REG_OPCODE_1_CLK : string := "NONE";
    REG_OPCODE_1_CE : string := "CE0";
    REG_OPCODE_1_RST : string := "RST0";
    REG_INPUTCFB_CLK : string := "NONE";
    REG_INPUTCFB_CE : string := "CE0";
    REG_INPUTCFB_RST : string := "RST0";
    CLK0_DIV : string := "ENABLED";
    CLK1_DIV : string := "ENABLED";
    CLK2_DIV : string := "ENABLED";
    CLK3_DIV : string := "ENABLED";
    GSR : string := "ENABLED";
    RESETMODE : string := "SYNC"  );
  port (
    CE3 :   in  std_logic;
    CE2 :   in  std_logic;
    CE1 :   in  std_logic;
    CE0 :   in  std_logic;
    CLK3 :   in  std_logic;
    CLK2 :   in  std_logic;
    CLK1 :   in  std_logic;
    CLK0 :   in  std_logic;
    RST3 :   in  std_logic;
    RST2 :   in  std_logic;
    RST1 :   in  std_logic;
    RST0 :   in  std_logic;
    SIGNEDIA :   in  std_logic;
    SIGNEDIB :   in  std_logic;
    MA17 :   in  std_logic;
    MA16 :   in  std_logic;
    MA15 :   in  std_logic;
    MA14 :   in  std_logic;
    MA13 :   in  std_logic;
    MA12 :   in  std_logic;
    MA11 :   in  std_logic;
    MA10 :   in  std_logic;
    MA9 :   in  std_logic;
    MA8 :   in  std_logic;
    MA7 :   in  std_logic;
    MA6 :   in  std_logic;
    MA5 :   in  std_logic;
    MA4 :   in  std_logic;
    MA3 :   in  std_logic;
    MA2 :   in  std_logic;
    MA1 :   in  std_logic;
    MA0 :   in  std_logic;
    MB17 :   in  std_logic;
    MB16 :   in  std_logic;
    MB15 :   in  std_logic;
    MB14 :   in  std_logic;
    MB13 :   in  std_logic;
    MB12 :   in  std_logic;
    MB11 :   in  std_logic;
    MB10 :   in  std_logic;
    MB9 :   in  std_logic;
    MB8 :   in  std_logic;
    MB7 :   in  std_logic;
    MB6 :   in  std_logic;
    MB5 :   in  std_logic;
    MB4 :   in  std_logic;
    MB3 :   in  std_logic;
    MB2 :   in  std_logic;
    MB1 :   in  std_logic;
    MB0 :   in  std_logic;
    CFB23 :   in  std_logic;
    CFB22 :   in  std_logic;
    CFB21 :   in  std_logic;
    CFB20 :   in  std_logic;
    CFB19 :   in  std_logic;
    CFB18 :   in  std_logic;
    CFB17 :   in  std_logic;
    CFB16 :   in  std_logic;
    CFB15 :   in  std_logic;
    CFB14 :   in  std_logic;
    CFB13 :   in  std_logic;
    CFB12 :   in  std_logic;
    CFB11 :   in  std_logic;
    CFB10 :   in  std_logic;
    CFB9 :   in  std_logic;
    CFB8 :   in  std_logic;
    CFB7 :   in  std_logic;
    CFB6 :   in  std_logic;
    CFB5 :   in  std_logic;
    CFB4 :   in  std_logic;
    CFB3 :   in  std_logic;
    CFB2 :   in  std_logic;
    CFB1 :   in  std_logic;
    CFB0 :   in  std_logic;
    CIN23 :   in  std_logic;
    CIN22 :   in  std_logic;
    CIN21 :   in  std_logic;
    CIN20 :   in  std_logic;
    CIN19 :   in  std_logic;
    CIN18 :   in  std_logic;
    CIN17 :   in  std_logic;
    CIN16 :   in  std_logic;
    CIN15 :   in  std_logic;
    CIN14 :   in  std_logic;
    CIN13 :   in  std_logic;
    CIN12 :   in  std_logic;
    CIN11 :   in  std_logic;
    CIN10 :   in  std_logic;
    CIN9 :   in  std_logic;
    CIN8 :   in  std_logic;
    CIN7 :   in  std_logic;
    CIN6 :   in  std_logic;
    CIN5 :   in  std_logic;
    CIN4 :   in  std_logic;
    CIN3 :   in  std_logic;
    CIN2 :   in  std_logic;
    CIN1 :   in  std_logic;
    CIN0 :   in  std_logic;
    OPADDNSUB :   in  std_logic;
    OPCINSEL :   in  std_logic;
    R23 :   out  std_logic;
    R22 :   out  std_logic;
    R21 :   out  std_logic;
    R20 :   out  std_logic;
    R19 :   out  std_logic;
    R18 :   out  std_logic;
    R17 :   out  std_logic;
    R16 :   out  std_logic;
    R15 :   out  std_logic;
    R14 :   out  std_logic;
    R13 :   out  std_logic;
    R12 :   out  std_logic;
    R11 :   out  std_logic;
    R10 :   out  std_logic;
    R9 :   out  std_logic;
    R8 :   out  std_logic;
    R7 :   out  std_logic;
    R6 :   out  std_logic;
    R5 :   out  std_logic;
    R4 :   out  std_logic;
    R3 :   out  std_logic;
    R2 :   out  std_logic;
    R1 :   out  std_logic;
    R0 :   out  std_logic;
    CO23 :   out  std_logic;
    CO22 :   out  std_logic;
    CO21 :   out  std_logic;
    CO20 :   out  std_logic;
    CO19 :   out  std_logic;
    CO18 :   out  std_logic;
    CO17 :   out  std_logic;
    CO16 :   out  std_logic;
    CO15 :   out  std_logic;
    CO14 :   out  std_logic;
    CO13 :   out  std_logic;
    CO12 :   out  std_logic;
    CO11 :   out  std_logic;
    CO10 :   out  std_logic;
    CO9 :   out  std_logic;
    CO8 :   out  std_logic;
    CO7 :   out  std_logic;
    CO6 :   out  std_logic;
    CO5 :   out  std_logic;
    CO4 :   out  std_logic;
    CO3 :   out  std_logic;
    CO2 :   out  std_logic;
    CO1 :   out  std_logic;
    CO0 :   out  std_logic  );
end component;

component ALU54B is
  generic (
    REG_INPUTC0_CLK : string := "NONE";
    REG_INPUTC0_CE : string := "CE0";
    REG_INPUTC0_RST : string := "RST0";
    REG_INPUTC1_CLK : string := "NONE";
    REG_INPUTC1_CE : string := "CE0";
    REG_INPUTC1_RST : string := "RST0";
    REG_OPCODEOP0_0_CLK : string := "NONE";
    REG_OPCODEOP0_0_CE : string := "CE0";
    REG_OPCODEOP0_0_RST : string := "RST0";
    REG_OPCODEOP1_0_CLK : string := "NONE";
    REG_OPCODEOP0_1_CLK : string := "NONE";
    REG_OPCODEOP0_1_CE : string := "CE0";
    REG_OPCODEOP0_1_RST : string := "RST0";
    REG_OPCODEOP1_1_CLK : string := "NONE";
    REG_OPCODEIN_0_CLK : string := "NONE";
    REG_OPCODEIN_0_CE : string := "CE0";
    REG_OPCODEIN_0_RST : string := "RST0";
    REG_OPCODEIN_1_CLK : string := "NONE";
    REG_OPCODEIN_1_CE : string := "CE0";
    REG_OPCODEIN_1_RST : string := "RST0";
    REG_OUTPUT0_CLK : string := "NONE";
    REG_OUTPUT0_CE : string := "CE0";
    REG_OUTPUT0_RST : string := "RST0";
    REG_OUTPUT1_CLK : string := "NONE";
    REG_OUTPUT1_CE : string := "CE0";
    REG_OUTPUT1_RST : string := "RST0";
    REG_FLAG_CLK : string := "NONE";
    REG_FLAG_CE : string := "CE0";
    REG_FLAG_RST : string := "RST0";
    MCPAT_SOURCE : string := "STATIC";
    MASKPAT_SOURCE : string := "STATIC";
    MASK01 : string := "0x00000000000000";
    REG_INPUTCFB_CLK : string := "NONE";
    REG_INPUTCFB_CE : string := "CE0";
    REG_INPUTCFB_RST : string := "RST0";
    CLK0_DIV : string := "ENABLED";
    CLK1_DIV : string := "ENABLED";
    CLK2_DIV : string := "ENABLED";
    CLK3_DIV : string := "ENABLED";
    MCPAT : string := "0x00000000000000";
    MASKPAT : string := "0x00000000000000";
    RNDPAT : string := "0x00000000000000";
    GSR : string := "ENABLED";
    RESETMODE : string := "SYNC";
    MULT9_MODE : string := "DISABLED";
    LEGACY : string := "DISABLED"  );
  port (
    CE3 :   in  std_logic;
    CE2 :   in  std_logic;
    CE1 :   in  std_logic;
    CE0 :   in  std_logic;
    CLK3 :   in  std_logic;
    CLK2 :   in  std_logic;
    CLK1 :   in  std_logic;
    CLK0 :   in  std_logic;
    RST3 :   in  std_logic;
    RST2 :   in  std_logic;
    RST1 :   in  std_logic;
    RST0 :   in  std_logic;
    SIGNEDIA :   in  std_logic;
    SIGNEDIB :   in  std_logic;
    SIGNEDCIN :   in  std_logic;
    A35 :   in  std_logic;
    A34 :   in  std_logic;
    A33 :   in  std_logic;
    A32 :   in  std_logic;
    A31 :   in  std_logic;
    A30 :   in  std_logic;
    A29 :   in  std_logic;
    A28 :   in  std_logic;
    A27 :   in  std_logic;
    A26 :   in  std_logic;
    A25 :   in  std_logic;
    A24 :   in  std_logic;
    A23 :   in  std_logic;
    A22 :   in  std_logic;
    A21 :   in  std_logic;
    A20 :   in  std_logic;
    A19 :   in  std_logic;
    A18 :   in  std_logic;
    A17 :   in  std_logic;
    A16 :   in  std_logic;
    A15 :   in  std_logic;
    A14 :   in  std_logic;
    A13 :   in  std_logic;
    A12 :   in  std_logic;
    A11 :   in  std_logic;
    A10 :   in  std_logic;
    A9 :   in  std_logic;
    A8 :   in  std_logic;
    A7 :   in  std_logic;
    A6 :   in  std_logic;
    A5 :   in  std_logic;
    A4 :   in  std_logic;
    A3 :   in  std_logic;
    A2 :   in  std_logic;
    A1 :   in  std_logic;
    A0 :   in  std_logic;
    B35 :   in  std_logic;
    B34 :   in  std_logic;
    B33 :   in  std_logic;
    B32 :   in  std_logic;
    B31 :   in  std_logic;
    B30 :   in  std_logic;
    B29 :   in  std_logic;
    B28 :   in  std_logic;
    B27 :   in  std_logic;
    B26 :   in  std_logic;
    B25 :   in  std_logic;
    B24 :   in  std_logic;
    B23 :   in  std_logic;
    B22 :   in  std_logic;
    B21 :   in  std_logic;
    B20 :   in  std_logic;
    B19 :   in  std_logic;
    B18 :   in  std_logic;
    B17 :   in  std_logic;
    B16 :   in  std_logic;
    B15 :   in  std_logic;
    B14 :   in  std_logic;
    B13 :   in  std_logic;
    B12 :   in  std_logic;
    B11 :   in  std_logic;
    B10 :   in  std_logic;
    B9 :   in  std_logic;
    B8 :   in  std_logic;
    B7 :   in  std_logic;
    B6 :   in  std_logic;
    B5 :   in  std_logic;
    B4 :   in  std_logic;
    B3 :   in  std_logic;
    B2 :   in  std_logic;
    B1 :   in  std_logic;
    B0 :   in  std_logic;
    C53 :   in  std_logic;
    C52 :   in  std_logic;
    C51 :   in  std_logic;
    C50 :   in  std_logic;
    C49 :   in  std_logic;
    C48 :   in  std_logic;
    C47 :   in  std_logic;
    C46 :   in  std_logic;
    C45 :   in  std_logic;
    C44 :   in  std_logic;
    C43 :   in  std_logic;
    C42 :   in  std_logic;
    C41 :   in  std_logic;
    C40 :   in  std_logic;
    C39 :   in  std_logic;
    C38 :   in  std_logic;
    C37 :   in  std_logic;
    C36 :   in  std_logic;
    C35 :   in  std_logic;
    C34 :   in  std_logic;
    C33 :   in  std_logic;
    C32 :   in  std_logic;
    C31 :   in  std_logic;
    C30 :   in  std_logic;
    C29 :   in  std_logic;
    C28 :   in  std_logic;
    C27 :   in  std_logic;
    C26 :   in  std_logic;
    C25 :   in  std_logic;
    C24 :   in  std_logic;
    C23 :   in  std_logic;
    C22 :   in  std_logic;
    C21 :   in  std_logic;
    C20 :   in  std_logic;
    C19 :   in  std_logic;
    C18 :   in  std_logic;
    C17 :   in  std_logic;
    C16 :   in  std_logic;
    C15 :   in  std_logic;
    C14 :   in  std_logic;
    C13 :   in  std_logic;
    C12 :   in  std_logic;
    C11 :   in  std_logic;
    C10 :   in  std_logic;
    C9 :   in  std_logic;
    C8 :   in  std_logic;
    C7 :   in  std_logic;
    C6 :   in  std_logic;
    C5 :   in  std_logic;
    C4 :   in  std_logic;
    C3 :   in  std_logic;
    C2 :   in  std_logic;
    C1 :   in  std_logic;
    C0 :   in  std_logic;
    CFB53 :   in  std_logic;
    CFB52 :   in  std_logic;
    CFB51 :   in  std_logic;
    CFB50 :   in  std_logic;
    CFB49 :   in  std_logic;
    CFB48 :   in  std_logic;
    CFB47 :   in  std_logic;
    CFB46 :   in  std_logic;
    CFB45 :   in  std_logic;
    CFB44 :   in  std_logic;
    CFB43 :   in  std_logic;
    CFB42 :   in  std_logic;
    CFB41 :   in  std_logic;
    CFB40 :   in  std_logic;
    CFB39 :   in  std_logic;
    CFB38 :   in  std_logic;
    CFB37 :   in  std_logic;
    CFB36 :   in  std_logic;
    CFB35 :   in  std_logic;
    CFB34 :   in  std_logic;
    CFB33 :   in  std_logic;
    CFB32 :   in  std_logic;
    CFB31 :   in  std_logic;
    CFB30 :   in  std_logic;
    CFB29 :   in  std_logic;
    CFB28 :   in  std_logic;
    CFB27 :   in  std_logic;
    CFB26 :   in  std_logic;
    CFB25 :   in  std_logic;
    CFB24 :   in  std_logic;
    CFB23 :   in  std_logic;
    CFB22 :   in  std_logic;
    CFB21 :   in  std_logic;
    CFB20 :   in  std_logic;
    CFB19 :   in  std_logic;
    CFB18 :   in  std_logic;
    CFB17 :   in  std_logic;
    CFB16 :   in  std_logic;
    CFB15 :   in  std_logic;
    CFB14 :   in  std_logic;
    CFB13 :   in  std_logic;
    CFB12 :   in  std_logic;
    CFB11 :   in  std_logic;
    CFB10 :   in  std_logic;
    CFB9 :   in  std_logic;
    CFB8 :   in  std_logic;
    CFB7 :   in  std_logic;
    CFB6 :   in  std_logic;
    CFB5 :   in  std_logic;
    CFB4 :   in  std_logic;
    CFB3 :   in  std_logic;
    CFB2 :   in  std_logic;
    CFB1 :   in  std_logic;
    CFB0 :   in  std_logic;
    MA35 :   in  std_logic;
    MA34 :   in  std_logic;
    MA33 :   in  std_logic;
    MA32 :   in  std_logic;
    MA31 :   in  std_logic;
    MA30 :   in  std_logic;
    MA29 :   in  std_logic;
    MA28 :   in  std_logic;
    MA27 :   in  std_logic;
    MA26 :   in  std_logic;
    MA25 :   in  std_logic;
    MA24 :   in  std_logic;
    MA23 :   in  std_logic;
    MA22 :   in  std_logic;
    MA21 :   in  std_logic;
    MA20 :   in  std_logic;
    MA19 :   in  std_logic;
    MA18 :   in  std_logic;
    MA17 :   in  std_logic;
    MA16 :   in  std_logic;
    MA15 :   in  std_logic;
    MA14 :   in  std_logic;
    MA13 :   in  std_logic;
    MA12 :   in  std_logic;
    MA11 :   in  std_logic;
    MA10 :   in  std_logic;
    MA9 :   in  std_logic;
    MA8 :   in  std_logic;
    MA7 :   in  std_logic;
    MA6 :   in  std_logic;
    MA5 :   in  std_logic;
    MA4 :   in  std_logic;
    MA3 :   in  std_logic;
    MA2 :   in  std_logic;
    MA1 :   in  std_logic;
    MA0 :   in  std_logic;
    MB35 :   in  std_logic;
    MB34 :   in  std_logic;
    MB33 :   in  std_logic;
    MB32 :   in  std_logic;
    MB31 :   in  std_logic;
    MB30 :   in  std_logic;
    MB29 :   in  std_logic;
    MB28 :   in  std_logic;
    MB27 :   in  std_logic;
    MB26 :   in  std_logic;
    MB25 :   in  std_logic;
    MB24 :   in  std_logic;
    MB23 :   in  std_logic;
    MB22 :   in  std_logic;
    MB21 :   in  std_logic;
    MB20 :   in  std_logic;
    MB19 :   in  std_logic;
    MB18 :   in  std_logic;
    MB17 :   in  std_logic;
    MB16 :   in  std_logic;
    MB15 :   in  std_logic;
    MB14 :   in  std_logic;
    MB13 :   in  std_logic;
    MB12 :   in  std_logic;
    MB11 :   in  std_logic;
    MB10 :   in  std_logic;
    MB9 :   in  std_logic;
    MB8 :   in  std_logic;
    MB7 :   in  std_logic;
    MB6 :   in  std_logic;
    MB5 :   in  std_logic;
    MB4 :   in  std_logic;
    MB3 :   in  std_logic;
    MB2 :   in  std_logic;
    MB1 :   in  std_logic;
    MB0 :   in  std_logic;
    CIN53 :   in  std_logic;
    CIN52 :   in  std_logic;
    CIN51 :   in  std_logic;
    CIN50 :   in  std_logic;
    CIN49 :   in  std_logic;
    CIN48 :   in  std_logic;
    CIN47 :   in  std_logic;
    CIN46 :   in  std_logic;
    CIN45 :   in  std_logic;
    CIN44 :   in  std_logic;
    CIN43 :   in  std_logic;
    CIN42 :   in  std_logic;
    CIN41 :   in  std_logic;
    CIN40 :   in  std_logic;
    CIN39 :   in  std_logic;
    CIN38 :   in  std_logic;
    CIN37 :   in  std_logic;
    CIN36 :   in  std_logic;
    CIN35 :   in  std_logic;
    CIN34 :   in  std_logic;
    CIN33 :   in  std_logic;
    CIN32 :   in  std_logic;
    CIN31 :   in  std_logic;
    CIN30 :   in  std_logic;
    CIN29 :   in  std_logic;
    CIN28 :   in  std_logic;
    CIN27 :   in  std_logic;
    CIN26 :   in  std_logic;
    CIN25 :   in  std_logic;
    CIN24 :   in  std_logic;
    CIN23 :   in  std_logic;
    CIN22 :   in  std_logic;
    CIN21 :   in  std_logic;
    CIN20 :   in  std_logic;
    CIN19 :   in  std_logic;
    CIN18 :   in  std_logic;
    CIN17 :   in  std_logic;
    CIN16 :   in  std_logic;
    CIN15 :   in  std_logic;
    CIN14 :   in  std_logic;
    CIN13 :   in  std_logic;
    CIN12 :   in  std_logic;
    CIN11 :   in  std_logic;
    CIN10 :   in  std_logic;
    CIN9 :   in  std_logic;
    CIN8 :   in  std_logic;
    CIN7 :   in  std_logic;
    CIN6 :   in  std_logic;
    CIN5 :   in  std_logic;
    CIN4 :   in  std_logic;
    CIN3 :   in  std_logic;
    CIN2 :   in  std_logic;
    CIN1 :   in  std_logic;
    CIN0 :   in  std_logic;
    OP10 :   in  std_logic;
    OP9 :   in  std_logic;
    OP8 :   in  std_logic;
    OP7 :   in  std_logic;
    OP6 :   in  std_logic;
    OP5 :   in  std_logic;
    OP4 :   in  std_logic;
    OP3 :   in  std_logic;
    OP2 :   in  std_logic;
    OP1 :   in  std_logic;
    OP0 :   in  std_logic;
    R53 :   out  std_logic;
    R52 :   out  std_logic;
    R51 :   out  std_logic;
    R50 :   out  std_logic;
    R49 :   out  std_logic;
    R48 :   out  std_logic;
    R47 :   out  std_logic;
    R46 :   out  std_logic;
    R45 :   out  std_logic;
    R44 :   out  std_logic;
    R43 :   out  std_logic;
    R42 :   out  std_logic;
    R41 :   out  std_logic;
    R40 :   out  std_logic;
    R39 :   out  std_logic;
    R38 :   out  std_logic;
    R37 :   out  std_logic;
    R36 :   out  std_logic;
    R35 :   out  std_logic;
    R34 :   out  std_logic;
    R33 :   out  std_logic;
    R32 :   out  std_logic;
    R31 :   out  std_logic;
    R30 :   out  std_logic;
    R29 :   out  std_logic;
    R28 :   out  std_logic;
    R27 :   out  std_logic;
    R26 :   out  std_logic;
    R25 :   out  std_logic;
    R24 :   out  std_logic;
    R23 :   out  std_logic;
    R22 :   out  std_logic;
    R21 :   out  std_logic;
    R20 :   out  std_logic;
    R19 :   out  std_logic;
    R18 :   out  std_logic;
    R17 :   out  std_logic;
    R16 :   out  std_logic;
    R15 :   out  std_logic;
    R14 :   out  std_logic;
    R13 :   out  std_logic;
    R12 :   out  std_logic;
    R11 :   out  std_logic;
    R10 :   out  std_logic;
    R9 :   out  std_logic;
    R8 :   out  std_logic;
    R7 :   out  std_logic;
    R6 :   out  std_logic;
    R5 :   out  std_logic;
    R4 :   out  std_logic;
    R3 :   out  std_logic;
    R2 :   out  std_logic;
    R1 :   out  std_logic;
    R0 :   out  std_logic;
    CO53 :   out  std_logic;
    CO52 :   out  std_logic;
    CO51 :   out  std_logic;
    CO50 :   out  std_logic;
    CO49 :   out  std_logic;
    CO48 :   out  std_logic;
    CO47 :   out  std_logic;
    CO46 :   out  std_logic;
    CO45 :   out  std_logic;
    CO44 :   out  std_logic;
    CO43 :   out  std_logic;
    CO42 :   out  std_logic;
    CO41 :   out  std_logic;
    CO40 :   out  std_logic;
    CO39 :   out  std_logic;
    CO38 :   out  std_logic;
    CO37 :   out  std_logic;
    CO36 :   out  std_logic;
    CO35 :   out  std_logic;
    CO34 :   out  std_logic;
    CO33 :   out  std_logic;
    CO32 :   out  std_logic;
    CO31 :   out  std_logic;
    CO30 :   out  std_logic;
    CO29 :   out  std_logic;
    CO28 :   out  std_logic;
    CO27 :   out  std_logic;
    CO26 :   out  std_logic;
    CO25 :   out  std_logic;
    CO24 :   out  std_logic;
    CO23 :   out  std_logic;
    CO22 :   out  std_logic;
    CO21 :   out  std_logic;
    CO20 :   out  std_logic;
    CO19 :   out  std_logic;
    CO18 :   out  std_logic;
    CO17 :   out  std_logic;
    CO16 :   out  std_logic;
    CO15 :   out  std_logic;
    CO14 :   out  std_logic;
    CO13 :   out  std_logic;
    CO12 :   out  std_logic;
    CO11 :   out  std_logic;
    CO10 :   out  std_logic;
    CO9 :   out  std_logic;
    CO8 :   out  std_logic;
    CO7 :   out  std_logic;
    CO6 :   out  std_logic;
    CO5 :   out  std_logic;
    CO4 :   out  std_logic;
    CO3 :   out  std_logic;
    CO2 :   out  std_logic;
    CO1 :   out  std_logic;
    CO0 :   out  std_logic;
    EQZ :   out  std_logic;
    EQZM :   out  std_logic;
    EQOM :   out  std_logic;
    EQPAT :   out  std_logic;
    EQPATB :   out  std_logic;
    OVER :   out  std_logic;
    UNDER :   out  std_logic;
    OVERUNDER :   out  std_logic;
    SIGNEDR :   out  std_logic  );
end component;

component PRADD9A is
  generic (
    REG_INPUTA_CLK : string := "NONE";
    REG_INPUTA_CE : string := "CE0";
    REG_INPUTA_RST : string := "RST0";
    REG_INPUTB_CLK : string := "NONE";
    REG_INPUTB_CE : string := "CE0";
    REG_INPUTB_RST : string := "RST0";
    REG_INPUTC_CLK : string := "NONE";
    REG_INPUTC_CE : string := "CE0";
    REG_INPUTC_RST : string := "RST0";
    REG_OPPRE_CLK : string := "NONE";
    REG_OPPRE_CE : string := "CE0";
    REG_OPPRE_RST : string := "RST0";
    CLK0_DIV : string := "ENABLED";
    CLK1_DIV : string := "ENABLED";
    CLK2_DIV : string := "ENABLED";
    CLK3_DIV : string := "ENABLED";
    HIGHSPEED_CLK : string := "NONE";
    GSR : string := "ENABLED";
    CAS_MATCH_REG : string := "FALSE";
    SOURCEA_MODE : string := "A_SHIFT";
    SOURCEB_MODE : string := "SHIFT";
    FB_MUX : string := "SHIFT";
    RESETMODE : string := "SYNC";
    SYMMETRY_MODE : string := "DIRECT"  );
  port (
    PA8 :   in  std_logic;
    PA7 :   in  std_logic;
    PA6 :   in  std_logic;
    PA5 :   in  std_logic;
    PA4 :   in  std_logic;
    PA3 :   in  std_logic;
    PA2 :   in  std_logic;
    PA1 :   in  std_logic;
    PA0 :   in  std_logic;
    PB8 :   in  std_logic;
    PB7 :   in  std_logic;
    PB6 :   in  std_logic;
    PB5 :   in  std_logic;
    PB4 :   in  std_logic;
    PB3 :   in  std_logic;
    PB2 :   in  std_logic;
    PB1 :   in  std_logic;
    PB0 :   in  std_logic;
    SRIA8 :   in  std_logic;
    SRIA7 :   in  std_logic;
    SRIA6 :   in  std_logic;
    SRIA5 :   in  std_logic;
    SRIA4 :   in  std_logic;
    SRIA3 :   in  std_logic;
    SRIA2 :   in  std_logic;
    SRIA1 :   in  std_logic;
    SRIA0 :   in  std_logic;
    SRIB8 :   in  std_logic;
    SRIB7 :   in  std_logic;
    SRIB6 :   in  std_logic;
    SRIB5 :   in  std_logic;
    SRIB4 :   in  std_logic;
    SRIB3 :   in  std_logic;
    SRIB2 :   in  std_logic;
    SRIB1 :   in  std_logic;
    SRIB0 :   in  std_logic;
    C8 :   in  std_logic;
    C7 :   in  std_logic;
    C6 :   in  std_logic;
    C5 :   in  std_logic;
    C4 :   in  std_logic;
    C3 :   in  std_logic;
    C2 :   in  std_logic;
    C1 :   in  std_logic;
    C0 :   in  std_logic;
    SOURCEA :   in  std_logic;
    OPPRE :   in  std_logic;
    CLK3 :   in  std_logic;
    CLK2 :   in  std_logic;
    CLK1 :   in  std_logic;
    CLK0 :   in  std_logic;
    CE3 :   in  std_logic;
    CE2 :   in  std_logic;
    CE1 :   in  std_logic;
    CE0 :   in  std_logic;
    RST3 :   in  std_logic;
    RST2 :   in  std_logic;
    RST1 :   in  std_logic;
    RST0 :   in  std_logic;
    SROA8 :   out  std_logic;
    SROA7 :   out  std_logic;
    SROA6 :   out  std_logic;
    SROA5 :   out  std_logic;
    SROA4 :   out  std_logic;
    SROA3 :   out  std_logic;
    SROA2 :   out  std_logic;
    SROA1 :   out  std_logic;
    SROA0 :   out  std_logic;
    SROB8 :   out  std_logic;
    SROB7 :   out  std_logic;
    SROB6 :   out  std_logic;
    SROB5 :   out  std_logic;
    SROB4 :   out  std_logic;
    SROB3 :   out  std_logic;
    SROB2 :   out  std_logic;
    SROB1 :   out  std_logic;
    SROB0 :   out  std_logic;
    PO8 :   out  std_logic;
    PO7 :   out  std_logic;
    PO6 :   out  std_logic;
    PO5 :   out  std_logic;
    PO4 :   out  std_logic;
    PO3 :   out  std_logic;
    PO2 :   out  std_logic;
    PO1 :   out  std_logic;
    PO0 :   out  std_logic  );
end component;

component PRADD18A is
  generic (
    REG_INPUTA_CLK : string := "NONE";
    REG_INPUTA_CE : string := "CE0";
    REG_INPUTA_RST : string := "RST0";
    REG_INPUTB_CLK : string := "NONE";
    REG_INPUTB_CE : string := "CE0";
    REG_INPUTB_RST : string := "RST0";
    REG_INPUTC_CLK : string := "NONE";
    REG_INPUTC_CE : string := "CE0";
    REG_INPUTC_RST : string := "RST0";
    REG_OPPRE_CLK : string := "NONE";
    REG_OPPRE_CE : string := "CE0";
    REG_OPPRE_RST : string := "RST0";
    CLK0_DIV : string := "ENABLED";
    CLK1_DIV : string := "ENABLED";
    CLK2_DIV : string := "ENABLED";
    CLK3_DIV : string := "ENABLED";
    HIGHSPEED_CLK : string := "NONE";
    GSR : string := "ENABLED";
    CAS_MATCH_REG : string := "FALSE";
    SOURCEA_MODE : string := "A_SHIFT";
    SOURCEB_MODE : string := "SHIFT";
    FB_MUX : string := "SHIFT";
    RESETMODE : string := "SYNC";
    SYMMETRY_MODE : string := "DIRECT"  );
  port (
    PA17 :   in  std_logic;
    PA16 :   in  std_logic;
    PA15 :   in  std_logic;
    PA14 :   in  std_logic;
    PA13 :   in  std_logic;
    PA12 :   in  std_logic;
    PA11 :   in  std_logic;
    PA10 :   in  std_logic;
    PA9 :   in  std_logic;
    PA8 :   in  std_logic;
    PA7 :   in  std_logic;
    PA6 :   in  std_logic;
    PA5 :   in  std_logic;
    PA4 :   in  std_logic;
    PA3 :   in  std_logic;
    PA2 :   in  std_logic;
    PA1 :   in  std_logic;
    PA0 :   in  std_logic;
    PB17 :   in  std_logic;
    PB16 :   in  std_logic;
    PB15 :   in  std_logic;
    PB14 :   in  std_logic;
    PB13 :   in  std_logic;
    PB12 :   in  std_logic;
    PB11 :   in  std_logic;
    PB10 :   in  std_logic;
    PB9 :   in  std_logic;
    PB8 :   in  std_logic;
    PB7 :   in  std_logic;
    PB6 :   in  std_logic;
    PB5 :   in  std_logic;
    PB4 :   in  std_logic;
    PB3 :   in  std_logic;
    PB2 :   in  std_logic;
    PB1 :   in  std_logic;
    PB0 :   in  std_logic;
    SRIA17 :   in  std_logic;
    SRIA16 :   in  std_logic;
    SRIA15 :   in  std_logic;
    SRIA14 :   in  std_logic;
    SRIA13 :   in  std_logic;
    SRIA12 :   in  std_logic;
    SRIA11 :   in  std_logic;
    SRIA10 :   in  std_logic;
    SRIA9 :   in  std_logic;
    SRIA8 :   in  std_logic;
    SRIA7 :   in  std_logic;
    SRIA6 :   in  std_logic;
    SRIA5 :   in  std_logic;
    SRIA4 :   in  std_logic;
    SRIA3 :   in  std_logic;
    SRIA2 :   in  std_logic;
    SRIA1 :   in  std_logic;
    SRIA0 :   in  std_logic;
    SRIB17 :   in  std_logic;
    SRIB16 :   in  std_logic;
    SRIB15 :   in  std_logic;
    SRIB14 :   in  std_logic;
    SRIB13 :   in  std_logic;
    SRIB12 :   in  std_logic;
    SRIB11 :   in  std_logic;
    SRIB10 :   in  std_logic;
    SRIB9 :   in  std_logic;
    SRIB8 :   in  std_logic;
    SRIB7 :   in  std_logic;
    SRIB6 :   in  std_logic;
    SRIB5 :   in  std_logic;
    SRIB4 :   in  std_logic;
    SRIB3 :   in  std_logic;
    SRIB2 :   in  std_logic;
    SRIB1 :   in  std_logic;
    SRIB0 :   in  std_logic;
    C17 :   in  std_logic;
    C16 :   in  std_logic;
    C15 :   in  std_logic;
    C14 :   in  std_logic;
    C13 :   in  std_logic;
    C12 :   in  std_logic;
    C11 :   in  std_logic;
    C10 :   in  std_logic;
    C9 :   in  std_logic;
    C8 :   in  std_logic;
    C7 :   in  std_logic;
    C6 :   in  std_logic;
    C5 :   in  std_logic;
    C4 :   in  std_logic;
    C3 :   in  std_logic;
    C2 :   in  std_logic;
    C1 :   in  std_logic;
    C0 :   in  std_logic;
    SOURCEA :   in  std_logic;
    OPPRE :   in  std_logic;
    CLK3 :   in  std_logic;
    CLK2 :   in  std_logic;
    CLK1 :   in  std_logic;
    CLK0 :   in  std_logic;
    CE3 :   in  std_logic;
    CE2 :   in  std_logic;
    CE1 :   in  std_logic;
    CE0 :   in  std_logic;
    RST3 :   in  std_logic;
    RST2 :   in  std_logic;
    RST1 :   in  std_logic;
    RST0 :   in  std_logic;
    SROA17 :   out  std_logic;
    SROA16 :   out  std_logic;
    SROA15 :   out  std_logic;
    SROA14 :   out  std_logic;
    SROA13 :   out  std_logic;
    SROA12 :   out  std_logic;
    SROA11 :   out  std_logic;
    SROA10 :   out  std_logic;
    SROA9 :   out  std_logic;
    SROA8 :   out  std_logic;
    SROA7 :   out  std_logic;
    SROA6 :   out  std_logic;
    SROA5 :   out  std_logic;
    SROA4 :   out  std_logic;
    SROA3 :   out  std_logic;
    SROA2 :   out  std_logic;
    SROA1 :   out  std_logic;
    SROA0 :   out  std_logic;
    SROB17 :   out  std_logic;
    SROB16 :   out  std_logic;
    SROB15 :   out  std_logic;
    SROB14 :   out  std_logic;
    SROB13 :   out  std_logic;
    SROB12 :   out  std_logic;
    SROB11 :   out  std_logic;
    SROB10 :   out  std_logic;
    SROB9 :   out  std_logic;
    SROB8 :   out  std_logic;
    SROB7 :   out  std_logic;
    SROB6 :   out  std_logic;
    SROB5 :   out  std_logic;
    SROB4 :   out  std_logic;
    SROB3 :   out  std_logic;
    SROB2 :   out  std_logic;
    SROB1 :   out  std_logic;
    SROB0 :   out  std_logic;
    PO17 :   out  std_logic;
    PO16 :   out  std_logic;
    PO15 :   out  std_logic;
    PO14 :   out  std_logic;
    PO13 :   out  std_logic;
    PO12 :   out  std_logic;
    PO11 :   out  std_logic;
    PO10 :   out  std_logic;
    PO9 :   out  std_logic;
    PO8 :   out  std_logic;
    PO7 :   out  std_logic;
    PO6 :   out  std_logic;
    PO5 :   out  std_logic;
    PO4 :   out  std_logic;
    PO3 :   out  std_logic;
    PO2 :   out  std_logic;
    PO1 :   out  std_logic;
    PO0 :   out  std_logic  );
end component;

component DP16KD is
  generic (
    DATA_WIDTH_A : integer := 18;
    DATA_WIDTH_B : integer := 18;
    REGMODE_A : string := "NOREG";
    REGMODE_B : string := "NOREG";
    RESETMODE : string := "SYNC";
    ASYNC_RESET_RELEASE : string := "SYNC";
    WRITEMODE_A : string := "NORMAL";
    WRITEMODE_B : string := "NORMAL";
    CSDECODE_A : string := "0b000";
    CSDECODE_B : string := "0b000";
    GSR : string := "ENABLED";
    INITVAL_00 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_01 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_02 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_03 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_04 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_05 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_06 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_07 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_08 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_09 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_0A : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_0B : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_0C : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_0D : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_0E : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_0F : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_10 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_11 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_12 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_13 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_14 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_15 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_16 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_17 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_18 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_19 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_1A : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_1B : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_1C : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_1D : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_1E : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_1F : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_20 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_21 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_22 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_23 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_24 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_25 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_26 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_27 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_28 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_29 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_2A : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_2B : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_2C : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_2D : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_2E : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_2F : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_30 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_31 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_32 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_33 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_34 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_35 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_36 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_37 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_38 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_39 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_3A : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_3B : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_3C : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_3D : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_3E : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_3F : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INIT_DATA : string := "STATIC"  );
  port (
    DIA17 :   in  std_logic;
    DIA16 :   in  std_logic;
    DIA15 :   in  std_logic;
    DIA14 :   in  std_logic;
    DIA13 :   in  std_logic;
    DIA12 :   in  std_logic;
    DIA11 :   in  std_logic;
    DIA10 :   in  std_logic;
    DIA9 :   in  std_logic;
    DIA8 :   in  std_logic;
    DIA7 :   in  std_logic;
    DIA6 :   in  std_logic;
    DIA5 :   in  std_logic;
    DIA4 :   in  std_logic;
    DIA3 :   in  std_logic;
    DIA2 :   in  std_logic;
    DIA1 :   in  std_logic;
    DIA0 :   in  std_logic;
    ADA13 :   in  std_logic;
    ADA12 :   in  std_logic;
    ADA11 :   in  std_logic;
    ADA10 :   in  std_logic;
    ADA9 :   in  std_logic;
    ADA8 :   in  std_logic;
    ADA7 :   in  std_logic;
    ADA6 :   in  std_logic;
    ADA5 :   in  std_logic;
    ADA4 :   in  std_logic;
    ADA3 :   in  std_logic;
    ADA2 :   in  std_logic;
    ADA1 :   in  std_logic;
    ADA0 :   in  std_logic;
    CEA :   in  std_logic;
    OCEA :   in  std_logic;
    CLKA :   in  std_logic;
    WEA :   in  std_logic;
    CSA2 :   in  std_logic;
    CSA1 :   in  std_logic;
    CSA0 :   in  std_logic;
    RSTA :   in  std_logic;
    DIB17 :   in  std_logic;
    DIB16 :   in  std_logic;
    DIB15 :   in  std_logic;
    DIB14 :   in  std_logic;
    DIB13 :   in  std_logic;
    DIB12 :   in  std_logic;
    DIB11 :   in  std_logic;
    DIB10 :   in  std_logic;
    DIB9 :   in  std_logic;
    DIB8 :   in  std_logic;
    DIB7 :   in  std_logic;
    DIB6 :   in  std_logic;
    DIB5 :   in  std_logic;
    DIB4 :   in  std_logic;
    DIB3 :   in  std_logic;
    DIB2 :   in  std_logic;
    DIB1 :   in  std_logic;
    DIB0 :   in  std_logic;
    ADB13 :   in  std_logic;
    ADB12 :   in  std_logic;
    ADB11 :   in  std_logic;
    ADB10 :   in  std_logic;
    ADB9 :   in  std_logic;
    ADB8 :   in  std_logic;
    ADB7 :   in  std_logic;
    ADB6 :   in  std_logic;
    ADB5 :   in  std_logic;
    ADB4 :   in  std_logic;
    ADB3 :   in  std_logic;
    ADB2 :   in  std_logic;
    ADB1 :   in  std_logic;
    ADB0 :   in  std_logic;
    CEB :   in  std_logic;
    OCEB :   in  std_logic;
    CLKB :   in  std_logic;
    WEB :   in  std_logic;
    CSB2 :   in  std_logic;
    CSB1 :   in  std_logic;
    CSB0 :   in  std_logic;
    RSTB :   in  std_logic;
    DOA17 :   out  std_logic;
    DOA16 :   out  std_logic;
    DOA15 :   out  std_logic;
    DOA14 :   out  std_logic;
    DOA13 :   out  std_logic;
    DOA12 :   out  std_logic;
    DOA11 :   out  std_logic;
    DOA10 :   out  std_logic;
    DOA9 :   out  std_logic;
    DOA8 :   out  std_logic;
    DOA7 :   out  std_logic;
    DOA6 :   out  std_logic;
    DOA5 :   out  std_logic;
    DOA4 :   out  std_logic;
    DOA3 :   out  std_logic;
    DOA2 :   out  std_logic;
    DOA1 :   out  std_logic;
    DOA0 :   out  std_logic;
    DOB17 :   out  std_logic;
    DOB16 :   out  std_logic;
    DOB15 :   out  std_logic;
    DOB14 :   out  std_logic;
    DOB13 :   out  std_logic;
    DOB12 :   out  std_logic;
    DOB11 :   out  std_logic;
    DOB10 :   out  std_logic;
    DOB9 :   out  std_logic;
    DOB8 :   out  std_logic;
    DOB7 :   out  std_logic;
    DOB6 :   out  std_logic;
    DOB5 :   out  std_logic;
    DOB4 :   out  std_logic;
    DOB3 :   out  std_logic;
    DOB2 :   out  std_logic;
    DOB1 :   out  std_logic;
    DOB0 :   out  std_logic  );
end component;

component PDPW16KD is
  generic (
    DATA_WIDTH_W : integer := 36;
    DATA_WIDTH_R : integer := 36;
    GSR : string := "ENABLED";
    REGMODE : string := "NOREG";
    RESETMODE : string := "SYNC";
    ASYNC_RESET_RELEASE : string := "SYNC";
    CSDECODE_W : string := "0b000";
    CSDECODE_R : string := "0b000";
    INITVAL_00 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_01 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_02 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_03 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_04 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_05 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_06 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_07 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_08 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_09 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_0A : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_0B : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_0C : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_0D : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_0E : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_0F : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_10 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_11 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_12 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_13 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_14 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_15 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_16 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_17 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_18 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_19 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_1A : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_1B : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_1C : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_1D : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_1E : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_1F : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_20 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_21 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_22 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_23 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_24 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_25 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_26 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_27 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_28 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_29 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_2A : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_2B : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_2C : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_2D : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_2E : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_2F : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_30 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_31 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_32 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_33 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_34 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_35 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_36 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_37 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_38 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_39 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_3A : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_3B : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_3C : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_3D : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_3E : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INITVAL_3F : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    INIT_DATA : string := "STATIC"  );
  port (
    DI35 :   in  std_logic;
    DI34 :   in  std_logic;
    DI33 :   in  std_logic;
    DI32 :   in  std_logic;
    DI31 :   in  std_logic;
    DI30 :   in  std_logic;
    DI29 :   in  std_logic;
    DI28 :   in  std_logic;
    DI27 :   in  std_logic;
    DI26 :   in  std_logic;
    DI25 :   in  std_logic;
    DI24 :   in  std_logic;
    DI23 :   in  std_logic;
    DI22 :   in  std_logic;
    DI21 :   in  std_logic;
    DI20 :   in  std_logic;
    DI19 :   in  std_logic;
    DI18 :   in  std_logic;
    DI17 :   in  std_logic;
    DI16 :   in  std_logic;
    DI15 :   in  std_logic;
    DI14 :   in  std_logic;
    DI13 :   in  std_logic;
    DI12 :   in  std_logic;
    DI11 :   in  std_logic;
    DI10 :   in  std_logic;
    DI9 :   in  std_logic;
    DI8 :   in  std_logic;
    DI7 :   in  std_logic;
    DI6 :   in  std_logic;
    DI5 :   in  std_logic;
    DI4 :   in  std_logic;
    DI3 :   in  std_logic;
    DI2 :   in  std_logic;
    DI1 :   in  std_logic;
    DI0 :   in  std_logic;
    ADW8 :   in  std_logic;
    ADW7 :   in  std_logic;
    ADW6 :   in  std_logic;
    ADW5 :   in  std_logic;
    ADW4 :   in  std_logic;
    ADW3 :   in  std_logic;
    ADW2 :   in  std_logic;
    ADW1 :   in  std_logic;
    ADW0 :   in  std_logic;
    BE3 :   in  std_logic;
    BE2 :   in  std_logic;
    BE1 :   in  std_logic;
    BE0 :   in  std_logic;
    CEW :   in  std_logic;
    CLKW :   in  std_logic;
    CSW2 :   in  std_logic;
    CSW1 :   in  std_logic;
    CSW0 :   in  std_logic;
    ADR13 :   in  std_logic;
    ADR12 :   in  std_logic;
    ADR11 :   in  std_logic;
    ADR10 :   in  std_logic;
    ADR9 :   in  std_logic;
    ADR8 :   in  std_logic;
    ADR7 :   in  std_logic;
    ADR6 :   in  std_logic;
    ADR5 :   in  std_logic;
    ADR4 :   in  std_logic;
    ADR3 :   in  std_logic;
    ADR2 :   in  std_logic;
    ADR1 :   in  std_logic;
    ADR0 :   in  std_logic;
    CER :   in  std_logic;
    OCER :   in  std_logic;
    CLKR :   in  std_logic;
    CSR2 :   in  std_logic;
    CSR1 :   in  std_logic;
    CSR0 :   in  std_logic;
    RST :   in  std_logic;
    DO35 :   out  std_logic;
    DO34 :   out  std_logic;
    DO33 :   out  std_logic;
    DO32 :   out  std_logic;
    DO31 :   out  std_logic;
    DO30 :   out  std_logic;
    DO29 :   out  std_logic;
    DO28 :   out  std_logic;
    DO27 :   out  std_logic;
    DO26 :   out  std_logic;
    DO25 :   out  std_logic;
    DO24 :   out  std_logic;
    DO23 :   out  std_logic;
    DO22 :   out  std_logic;
    DO21 :   out  std_logic;
    DO20 :   out  std_logic;
    DO19 :   out  std_logic;
    DO18 :   out  std_logic;
    DO17 :   out  std_logic;
    DO16 :   out  std_logic;
    DO15 :   out  std_logic;
    DO14 :   out  std_logic;
    DO13 :   out  std_logic;
    DO12 :   out  std_logic;
    DO11 :   out  std_logic;
    DO10 :   out  std_logic;
    DO9 :   out  std_logic;
    DO8 :   out  std_logic;
    DO7 :   out  std_logic;
    DO6 :   out  std_logic;
    DO5 :   out  std_logic;
    DO4 :   out  std_logic;
    DO3 :   out  std_logic;
    DO2 :   out  std_logic;
    DO1 :   out  std_logic;
    DO0 :   out  std_logic  );
end component;

component DPR16X4C is
  generic (
    INITVAL : string := "0x0000000000000000"  );
  port (
    DI3 :   in  std_logic;
    DI2 :   in  std_logic;
    DI1 :   in  std_logic;
    DI0 :   in  std_logic;
    WAD3 :   in  std_logic;
    WAD2 :   in  std_logic;
    WAD1 :   in  std_logic;
    WAD0 :   in  std_logic;
    WCK :   in  std_logic;
    WRE :   in  std_logic;
    RAD3 :   in  std_logic;
    RAD2 :   in  std_logic;
    RAD1 :   in  std_logic;
    RAD0 :   in  std_logic;
    DO3 :   out  std_logic;
    DO2 :   out  std_logic;
    DO1 :   out  std_logic;
    DO0 :   out  std_logic  );
end component;

component SPR16X4C is
  generic (
    INITVAL : string := "0x0000000000000000"  );
  port (
    DI3 :   in  std_logic;
    DI2 :   in  std_logic;
    DI1 :   in  std_logic;
    DI0 :   in  std_logic;
    AD3 :   in  std_logic;
    AD2 :   in  std_logic;
    AD1 :   in  std_logic;
    AD0 :   in  std_logic;
    CK :   in  std_logic;
    WRE :   in  std_logic;
    DO3 :   out  std_logic;
    DO2 :   out  std_logic;
    DO1 :   out  std_logic;
    DO0 :   out  std_logic  );
end component;

component DTR is
  generic (
    DTR_TEMP : integer := 25  );
  port (
    STARTPULSE :   in  std_logic;
    DTROUT7 :   out  std_logic;
    DTROUT6 :   out  std_logic;
    DTROUT5 :   out  std_logic;
    DTROUT4 :   out  std_logic;
    DTROUT3 :   out  std_logic;
    DTROUT2 :   out  std_logic;
    DTROUT1 :   out  std_logic;
    DTROUT0 :   out  std_logic  );
end component;

component CLKDIVF is
  generic (
    GSR : string := "DISABLED";
    DIV : string := "2.0"  );
  port (
    CLKI :   in  std_logic;
    RST :   in  std_logic;
    ALIGNWD :   in  std_logic;
    CDIVX :   out  std_logic  );
end component;

component PCSCLKDIV is
  generic (
    GSR : string := "DISABLED"  );
  port (
    CLKI :   in  std_logic;
    RST :   in  std_logic;
    SEL2 :   in  std_logic;
    SEL1 :   in  std_logic;
    SEL0 :   in  std_logic;
    CDIV1 :   out  std_logic;
    CDIVX :   out  std_logic  );
end component;

component DCSC is
  generic (
    DCSMODE : string := "POS"  );
  port (
    CLK1 :   in  std_logic;
    CLK0 :   in  std_logic;
    SEL1 :   in  std_logic;
    SEL0 :   in  std_logic;
    MODESEL :   in  std_logic;
    DCSOUT :   out  std_logic  );
end component;

component ECLKSYNCB is
  port (
    ECLKI :   in  std_logic;
    STOP :   in  std_logic;
    ECLKO :   out  std_logic  );
end component;

component ECLKBRIDGECS is
  port (
    CLK0 :   in  std_logic;
    CLK1 :   in  std_logic;
    SEL :   in  std_logic;
    ECSOUT :   out  std_logic  );
end component;

component DCCA is
  port (
    CLKI :   in  std_logic;
    CE :   in  std_logic;
    CLKO :   out  std_logic  );
end component;

component OSCG is
  generic (
    DIV : integer := 128  );
  port (
    OSC :   out  std_logic  );
end component;

component EHXPLLL is
  generic (
    CLKI_DIV : integer := 1;
    CLKFB_DIV : integer := 1;
    CLKOP_DIV : integer := 8;
    CLKOS_DIV : integer := 8;
    CLKOS2_DIV : integer := 8;
    CLKOS3_DIV : integer := 8;
    CLKOP_ENABLE : string := "ENABLED";
    CLKOS_ENABLE : string := "DISABLED";
    CLKOS2_ENABLE : string := "DISABLED";
    CLKOS3_ENABLE : string := "DISABLED";
    CLKOP_CPHASE : integer := 0;
    CLKOS_CPHASE : integer := 0;
    CLKOS2_CPHASE : integer := 0;
    CLKOS3_CPHASE : integer := 0;
    CLKOP_FPHASE : integer := 0;
    CLKOS_FPHASE : integer := 0;
    CLKOS2_FPHASE : integer := 0;
    CLKOS3_FPHASE : integer := 0;
    FEEDBK_PATH : string := "CLKOP";
    CLKOP_TRIM_POL : string := "RISING";
    CLKOP_TRIM_DELAY : integer := 0;
    CLKOS_TRIM_POL : string := "RISING";
    CLKOS_TRIM_DELAY : integer := 0;
    OUTDIVIDER_MUXA : string := "DIVA";
    OUTDIVIDER_MUXB : string := "DIVB";
    OUTDIVIDER_MUXC : string := "DIVC";
    OUTDIVIDER_MUXD : string := "DIVD";
    PLL_LOCK_MODE : integer := 0;
    PLL_LOCK_DELAY : integer := 200;
    STDBY_ENABLE : string := "DISABLED";
    REFIN_RESET : string := "DISABLED";
    SYNC_ENABLE : string := "DISABLED";
    INT_LOCK_STICKY : string := "ENABLED";
    DPHASE_SOURCE : string := "DISABLED";
    PLLRST_ENA : string := "DISABLED";
    INTFB_WAKE : string := "DISABLED"  );
  port (
    CLKI :   in  std_logic;
    CLKFB :   in  std_logic;
    PHASESEL1 :   in  std_logic;
    PHASESEL0 :   in  std_logic;
    PHASEDIR :   in  std_logic;
    PHASESTEP :   in  std_logic;
    PHASELOADREG :   in  std_logic;
    STDBY :   in  std_logic;
    PLLWAKESYNC :   in  std_logic;
    RST :   in  std_logic;
    ENCLKOP :   in  std_logic;
    ENCLKOS :   in  std_logic;
    ENCLKOS2 :   in  std_logic;
    ENCLKOS3 :   in  std_logic;
    CLKOP :   out  std_logic;
    CLKOS :   out  std_logic;
    CLKOS2 :   out  std_logic;
    CLKOS3 :   out  std_logic;
    LOCK :   out  std_logic;
    INTLOCK :   out  std_logic;
    REFCLK :   out  std_logic;
    CLKINTFB :   out  std_logic  );
end component;

component PLLREFCS is
  port (
    CLK0 :   in  std_logic;
    CLK1 :   in  std_logic;
    SEL :   in  std_logic;
    PLLCSOUT :   out  std_logic  );
end component;

component BCINRD is
  generic (
    BANKID : integer := 2  );
  port (
    INRDENI :   in  std_logic  );
end component;

component BCLVDSOB is
  generic (
    BANKID : integer := 2  );
  port (
    LVDSENI :   in  std_logic  );
end component;

component INRDB is
  port (
    D :   in  std_logic;
    E :   in  std_logic;
    Q :   out  std_logic  );
end component;

component LVDSOB is
  port (
    D :   in  std_logic;
    E :   in  std_logic;
    Q :   out  std_logic  );
end component;

component START is
  port (
    STARTCLK :   in  std_logic  );
end component;

component USRMCLK is
  port (
    USRMCLKI :   in  std_logic;
    USRMCLKTS :   in  std_logic  );
end component;

component DELAYF is
  generic (
    DEL_MODE : string := "USER_DEFINED";
    DEL_VALUE : integer := 0  );
  port (
    A :   in  std_logic;
    LOADN :   in  std_logic;
    MOVE :   in  std_logic;
    DIRECTION :   in  std_logic;
    Z :   out  std_logic;
    CFLAG :   out  std_logic  );
end component;

component DELAYG is
  generic (
    DEL_MODE : string := "USER_DEFINED";
    DEL_VALUE : integer := 0  );
  port (
    A :   in  std_logic;
    Z :   out  std_logic  );
end component;

component DQSBUFM is
  generic (
    DQS_LI_DEL_VAL : integer := 4;
    DQS_LI_DEL_ADJ : string := "FACTORYONLY";
    DQS_LO_DEL_VAL : integer := 0;
    DQS_LO_DEL_ADJ : string := "FACTORYONLY";
    GSR : string := "ENABLED"  );
  port (
    DQSI :   in  std_logic;
    READ1 :   in  std_logic;
    READ0 :   in  std_logic;
    READCLKSEL2 :   in  std_logic;
    READCLKSEL1 :   in  std_logic;
    READCLKSEL0 :   in  std_logic;
    DDRDEL :   in  std_logic;
    ECLK :   in  std_logic;
    SCLK :   in  std_logic;
    RST :   in  std_logic;
    DYNDELAY7 :   in  std_logic;
    DYNDELAY6 :   in  std_logic;
    DYNDELAY5 :   in  std_logic;
    DYNDELAY4 :   in  std_logic;
    DYNDELAY3 :   in  std_logic;
    DYNDELAY2 :   in  std_logic;
    DYNDELAY1 :   in  std_logic;
    DYNDELAY0 :   in  std_logic;
    PAUSE :   in  std_logic;
    RDLOADN :   in  std_logic;
    RDMOVE :   in  std_logic;
    RDDIRECTION :   in  std_logic;
    WRLOADN :   in  std_logic;
    WRMOVE :   in  std_logic;
    WRDIRECTION :   in  std_logic;
    DQSR90 :   out  std_logic;
    DQSW :   out  std_logic;
    DQSW270 :   out  std_logic;
    RDPNTR2 :   out  std_logic;
    RDPNTR1 :   out  std_logic;
    RDPNTR0 :   out  std_logic;
    WRPNTR2 :   out  std_logic;
    WRPNTR1 :   out  std_logic;
    WRPNTR0 :   out  std_logic;
    DATAVALID :   out  std_logic;
    BURSTDET :   out  std_logic;
    RDCFLAG :   out  std_logic;
    WRCFLAG :   out  std_logic  );
end component;

component DDRDLLA is
  generic (
    FORCE_MAX_DELAY : string := "NO";
    LOCK_CYC : integer := 200;
    GSR : string := "ENABLED"  );
  port (
    CLK :   in  std_logic;
    RST :   in  std_logic;
    UDDCNTLN :   in  std_logic;
    FREEZE :   in  std_logic;
    DDRDEL :   out  std_logic;
    LOCK :   out  std_logic;
    DCNTL7 :   out  std_logic;
    DCNTL6 :   out  std_logic;
    DCNTL5 :   out  std_logic;
    DCNTL4 :   out  std_logic;
    DCNTL3 :   out  std_logic;
    DCNTL2 :   out  std_logic;
    DCNTL1 :   out  std_logic;
    DCNTL0 :   out  std_logic  );
end component;

component DLLDELD is
  port (
    A :   in  std_logic;
    DDRDEL :   in  std_logic;
    LOADN :   in  std_logic;
    MOVE :   in  std_logic;
    DIRECTION :   in  std_logic;
    Z :   out  std_logic;
    CFLAG :   out  std_logic  );
end component;

component IDDRX1F is
  generic (
    GSR : string := "ENABLED"  );
  port (
    D :   in  std_logic;
    SCLK :   in  std_logic;
    RST :   in  std_logic;
    Q0 :   out  std_logic;
    Q1 :   out  std_logic  );
end component;

component IDDRX2F is
  generic (
    GSR : string := "ENABLED"  );
  port (
    D :   in  std_logic;
    SCLK :   in  std_logic;
    ECLK :   in  std_logic;
    RST :   in  std_logic;
    ALIGNWD :   in  std_logic;
    Q3 :   out  std_logic;
    Q2 :   out  std_logic;
    Q1 :   out  std_logic;
    Q0 :   out  std_logic  );
end component;

component IDDR71B is
  generic (
    GSR : string := "ENABLED"  );
  port (
    D :   in  std_logic;
    SCLK :   in  std_logic;
    ECLK :   in  std_logic;
    RST :   in  std_logic;
    ALIGNWD :   in  std_logic;
    Q6 :   out  std_logic;
    Q5 :   out  std_logic;
    Q4 :   out  std_logic;
    Q3 :   out  std_logic;
    Q2 :   out  std_logic;
    Q1 :   out  std_logic;
    Q0 :   out  std_logic  );
end component;

component ODDRX1F is
  generic (
    GSR : string := "ENABLED"  );
  port (
    SCLK :   in  std_logic;
    RST :   in  std_logic;
    D0 :   in  std_logic;
    D1 :   in  std_logic;
    Q :   out  std_logic  );
end component;

component ODDRX2F is
  generic (
    GSR : string := "ENABLED"  );
  port (
    SCLK :   in  std_logic;
    ECLK :   in  std_logic;
    RST :   in  std_logic;
    D3 :   in  std_logic;
    D2 :   in  std_logic;
    D1 :   in  std_logic;
    D0 :   in  std_logic;
    Q :   out  std_logic  );
end component;

component ODDR71B is
  generic (
    GSR : string := "ENABLED"  );
  port (
    SCLK :   in  std_logic;
    ECLK :   in  std_logic;
    RST :   in  std_logic;
    D6 :   in  std_logic;
    D5 :   in  std_logic;
    D4 :   in  std_logic;
    D3 :   in  std_logic;
    D2 :   in  std_logic;
    D1 :   in  std_logic;
    D0 :   in  std_logic;
    Q :   out  std_logic  );
end component;

component IMIPI is
  port (
    A :   in  std_logic;
    AN :   in  std_logic;
    HSSEL :   in  std_logic;
    OHSOLS1 :   out  std_logic;
    OLS0 :   out  std_logic  );
end component;

component IDDRX2DQA is
  generic (
    GSR : string := "ENABLED"  );
  port (
    SCLK :   in  std_logic;
    ECLK :   in  std_logic;
    DQSR90 :   in  std_logic;
    D :   in  std_logic;
    RST :   in  std_logic;
    RDPNTR2 :   in  std_logic;
    RDPNTR1 :   in  std_logic;
    RDPNTR0 :   in  std_logic;
    WRPNTR2 :   in  std_logic;
    WRPNTR1 :   in  std_logic;
    WRPNTR0 :   in  std_logic;
    Q3 :   out  std_logic;
    Q2 :   out  std_logic;
    Q1 :   out  std_logic;
    Q0 :   out  std_logic;
    QWL :   out  std_logic  );
end component;

component ODDRX2DQA is
  generic (
    GSR : string := "ENABLED"  );
  port (
    D3 :   in  std_logic;
    D2 :   in  std_logic;
    D1 :   in  std_logic;
    D0 :   in  std_logic;
    DQSW270 :   in  std_logic;
    SCLK :   in  std_logic;
    ECLK :   in  std_logic;
    RST :   in  std_logic;
    Q :   out  std_logic  );
end component;

component ODDRX2DQSB is
  generic (
    GSR : string := "ENABLED"  );
  port (
    D3 :   in  std_logic;
    D2 :   in  std_logic;
    D1 :   in  std_logic;
    D0 :   in  std_logic;
    SCLK :   in  std_logic;
    ECLK :   in  std_logic;
    DQSW :   in  std_logic;
    RST :   in  std_logic;
    Q :   out  std_logic  );
end component;

component TSHX2DQA is
  generic (
    GSR : string := "ENABLED";
    REGSET : string := "SET"  );
  port (
    T1 :   in  std_logic;
    T0 :   in  std_logic;
    SCLK :   in  std_logic;
    ECLK :   in  std_logic;
    DQSW270 :   in  std_logic;
    RST :   in  std_logic;
    Q :   out  std_logic  );
end component;

component TSHX2DQSA is
  generic (
    GSR : string := "ENABLED";
    REGSET : string := "SET"  );
  port (
    T1 :   in  std_logic;
    T0 :   in  std_logic;
    SCLK :   in  std_logic;
    ECLK :   in  std_logic;
    DQSW :   in  std_logic;
    RST :   in  std_logic;
    Q :   out  std_logic  );
end component;

component OSHX2A is
  generic (
    GSR : string := "ENABLED"  );
  port (
    D1 :   in  std_logic;
    D0 :   in  std_logic;
    SCLK :   in  std_logic;
    ECLK :   in  std_logic;
    RST :   in  std_logic;
    Q :   out  std_logic  );
end component;

component JTAGG is
  generic (
    ER1 : string := "ENABLED";
    ER2 : string := "ENABLED"  );
  port (
    TCK :   in  std_logic;
    TMS :   in  std_logic;
    TDI :   in  std_logic;
    JTDO2 :   in  std_logic;
    JTDO1 :   in  std_logic;
    TDO :   out  std_logic;
    JTDI :   out  std_logic;
    JTCK :   out  std_logic;
    JRTI2 :   out  std_logic;
    JRTI1 :   out  std_logic;
    JSHIFT :   out  std_logic;
    JUPDATE :   out  std_logic;
    JRSTN :   out  std_logic;
    JCE2 :   out  std_logic;
    JCE1 :   out  std_logic  );
end component;

component SEDGA is
  generic (
    SED_CLK_FREQ : string := "2.4";
    CHECKALWAYS : string := "DISABLED";
    DEV_DENSITY : string := "85KUM"  );
  port (
    SEDENABLE :   in  std_logic;
    SEDSTART :   in  std_logic;
    SEDFRCERR :   in  std_logic;
    SEDERR :   out  std_logic;
    SEDDONE :   out  std_logic;
    SEDINPROG :   out  std_logic;
    SEDCLKOUT :   out  std_logic  );
end component;

component EXTREFB is
  generic (
    REFCK_PWDNB : string := "DONTCARE";
    REFCK_RTERM : string := "DONTCARE";
    REFCK_DCBIAS_EN : string := "DONTCARE"  );
  port (
    REFCLKP :   in  std_logic;
    REFCLKN :   in  std_logic;
    REFCLKO :   out  std_logic  );
end component;

component PUR is
  generic (
    RST_PULSE : integer := 1  );
  port (
    PUR :   in  std_logic  );
end component;

component BUFBA is
  port (
    A :   in  std_logic;
    Z :   out  std_logic  );
end component;

component OBZPD is
  port (
    I :   in  std_logic;
    T :   in  std_logic;
    O :   out  std_logic  );
end component;

component SLOGICB is
  generic (
    TIMINGCHECKSON : boolean := true;
    XON : boolean := false;
    MSGON : boolean := true;
    INSTANCEPATH : string := "SLOGICB";
    GSR : string := "ENABLED";
    SRMODE : string := "LSR_OVER_CE";
    M1MUX : string := "VLO";
    M0MUX : string := "VLO";
    LSRMUX : string := "VLO";
    CEMUX : string := "VLO";
    CLKMUX : string := "VLO";
    REG1_SD : string := "VLO";
    REG0_SD : string := "VLO";
    LUT1_INITVAL : bit_vector := "0000000000000000";
    LUT0_INITVAL : bit_vector := "0000000000000000";
    REG1_REGSET : string := "RESET";
    REG0_REGSET : string := "RESET";
    LSRONMUX : string := "LSRMUX";
    CHECK_M1 : boolean := false;
    CHECK_DI1 : boolean := false;
    CHECK_DI0 : boolean := false;
    CHECK_M0 : boolean := false;
    CHECK_CE : boolean := false;
    CHECK_LSR : boolean := false  );
  port (
    M1 :   in  std_ulogic;
    FXA :   in  std_ulogic;
    FXB :   in  std_ulogic;
    A1 :   in  std_ulogic;
    B1 :   in  std_ulogic;
    C1 :   in  std_ulogic;
    D1 :   in  std_ulogic;
    DI1 :   in  std_ulogic;
    DI0 :   in  std_ulogic;
    A0 :   in  std_ulogic;
    B0 :   in  std_ulogic;
    C0 :   in  std_ulogic;
    D0 :   in  std_ulogic;
    M0 :   in  std_ulogic;
    CE :   in  std_ulogic;
    CLK :   in  std_ulogic;
    LSR :   in  std_ulogic;
    OFX1 :   out  std_ulogic;
    F1 :   out  std_ulogic;
    Q1 :   out  std_ulogic;
    OFX0 :   out  std_ulogic;
    F0 :   out  std_ulogic;
    Q0 :   out  std_ulogic  );
end component;

component SCCU2C is
  generic (
    TIMINGCHECKSON : boolean := true;
    XON : boolean := false;
    MSGON : boolean := true;
    INSTANCEPATH : string := "SCCU2C";
    GSR : string := "ENABLED";
    SRMODE : string := "LSR_OVER_CE";
    M1MUX : string := "VLO";
    M0MUX : string := "VLO";
    LSRMUX : string := "VLO";
    CEMUX : string := "VLO";
    CLKMUX : string := "VLO";
    REG1_SD : string := "VLO";
    REG0_SD : string := "VLO";
    REG1_REGSET : string := "RESET";
    REG0_REGSET : string := "RESET";
    LSRONMUX : string := "LSRMUX";
    CCU2_INJECT1_0 : string := "YES";
    CCU2_INJECT1_1 : string := "YES";
    INIT0_INITVAL : std_logic_vector := "0000000000000000";
    INIT1_INITVAL : std_logic_vector := "0000000000000000";
    CHECK_M1 : boolean := false;
    CHECK_DI1 : boolean := false;
    CHECK_DI0 : boolean := false;
    CHECK_M0 : boolean := false;
    CHECK_CE : boolean := false;
    CHECK_LSR : boolean := false  );
  port (
    M1 :   in  std_ulogic;
    A1 :   in  std_ulogic;
    B1 :   in  std_ulogic;
    C1 :   in  std_ulogic;
    D1 :   in  std_ulogic;
    DI1 :   in  std_ulogic;
    DI0 :   in  std_ulogic;
    A0 :   in  std_ulogic;
    B0 :   in  std_ulogic;
    C0 :   in  std_ulogic;
    D0 :   in  std_ulogic;
    FCI :   in  std_ulogic;
    M0 :   in  std_ulogic;
    CE :   in  std_ulogic;
    CLK :   in  std_ulogic;
    LSR :   in  std_ulogic;
    FCO :   out  std_ulogic;
    F1 :   out  std_ulogic;
    Q1 :   out  std_ulogic;
    F0 :   out  std_ulogic;
    Q0 :   out  std_ulogic  );
end component;

component SRAMWB is
  generic (
    TIMINGCHECKSON : boolean := true;
    XON : boolean := false;
    MSGON : boolean := true;
    INSTANCEPATH : string := "SRAMWB";
    WD0MUX : string := "VLO";
    WD1MUX : string := "VLO";
    WD2MUX : string := "VLO";
    WD3MUX : string := "VLO";
    WAD0MUX : string := "VLO";
    WAD1MUX : string := "VLO";
    WAD2MUX : string := "VLO";
    WAD3MUX : string := "VLO"  );
  port (
    A1 :   in  std_ulogic;
    B1 :   in  std_ulogic;
    C1 :   in  std_ulogic;
    D1 :   in  std_ulogic;
    A0 :   in  std_ulogic;
    B0 :   in  std_ulogic;
    C0 :   in  std_ulogic;
    D0 :   in  std_ulogic;
    WDO0 :   out  std_ulogic;
    WDO1 :   out  std_ulogic;
    WDO2 :   out  std_ulogic;
    WDO3 :   out  std_ulogic;
    WADO0 :   out  std_ulogic;
    WADO1 :   out  std_ulogic;
    WADO2 :   out  std_ulogic;
    WADO3 :   out  std_ulogic  );
end component;

component SDPRAME is
  generic (
    TIMINGCHECKSON : boolean := true;
    XON : boolean := false;
    MSGON : boolean := true;
    INSTANCEPATH : string := "SDPRAME";
    GSR : string := "ENABLED";
    SRMODE : string := "LSR_OVER_CE";
    M1MUX : string := "VLO";
    M0MUX : string := "VLO";
    LSRMUX : string := "VLO";
    CEMUX : string := "VLO";
    CLKMUX : string := "VLO";
    WREMUX : string := "VLO";
    WCKMUX : string := "VLO";
    REG1_SD : string := "VLO";
    REG0_SD : string := "VLO";
    REG1_REGSET : string := "RESET";
    REG0_REGSET : string := "RESET";
    LSRONMUX : string := "LSRMUX";
    INITVAL : string := "0x0000000000000000";
    DPRAM_RAD0 : string := "SIG";
    DPRAM_RAD1 : string := "SIG";
    DPRAM_RAD2 : string := "SIG";
    DPRAM_RAD3 : string := "SIG";
    CHECK_WD1 : boolean := false;
    CHECK_WD0 : boolean := false;
    CHECK_WAD0 : boolean := false;
    CHECK_WAD1 : boolean := false;
    CHECK_WAD2 : boolean := false;
    CHECK_WAD3 : boolean := false;
    CHECK_WRE : boolean := false;
    CHECK_M0 : boolean := false;
    CHECK_M1 : boolean := false;
    CHECK_CE : boolean := false;
    CHECK_LSR : boolean := false;
    CHECK_DI1 : boolean := false;
    CHECK_DI0 : boolean := false  );
  port (
    M1 :   in  std_ulogic;
    RAD0 :   in  std_ulogic;
    RAD1 :   in  std_ulogic;
    RAD2 :   in  std_ulogic;
    RAD3 :   in  std_ulogic;
    WD1 :   in  std_ulogic;
    WD0 :   in  std_ulogic;
    WAD0 :   in  std_ulogic;
    WAD1 :   in  std_ulogic;
    WAD2 :   in  std_ulogic;
    WAD3 :   in  std_ulogic;
    WRE :   in  std_ulogic;
    WCK :   in  std_ulogic;
    M0 :   in  std_ulogic;
    CE :   in  std_ulogic;
    CLK :   in  std_ulogic;
    LSR :   in  std_ulogic;
    DI1 :   in  std_ulogic;
    DI0 :   in  std_ulogic;
    F0 :   out  std_ulogic;
    Q0 :   out  std_ulogic;
    F1 :   out  std_ulogic;
    Q1 :   out  std_ulogic  );
end component;

component DCUA is
  generic (
    D_MACROPDB : string := "DONTCARE";
    D_IB_PWDNB : string := "DONTCARE";
    D_XGE_MODE : string := "DONTCARE";
    D_LOW_MARK : string := "DONTCARE";
    D_HIGH_MARK : string := "DONTCARE";
    D_BUS8BIT_SEL : string := "DONTCARE";
    D_CDR_LOL_SET : string := "DONTCARE";
    D_BITCLK_LOCAL_EN : string := "DONTCARE";
    D_BITCLK_ND_EN : string := "DONTCARE";
    D_BITCLK_FROM_ND_EN : string := "DONTCARE";
    D_SYNC_LOCAL_EN : string := "DONTCARE";
    D_SYNC_ND_EN : string := "DONTCARE";
    CH0_UC_MODE : string := "DONTCARE";
    CH1_UC_MODE : string := "DONTCARE";
    CH0_PCIE_MODE : string := "DONTCARE";
    CH1_PCIE_MODE : string := "DONTCARE";
    CH0_RIO_MODE : string := "DONTCARE";
    CH1_RIO_MODE : string := "DONTCARE";
    CH0_WA_MODE : string := "DONTCARE";
    CH1_WA_MODE : string := "DONTCARE";
    CH0_INVERT_RX : string := "DONTCARE";
    CH1_INVERT_RX : string := "DONTCARE";
    CH0_INVERT_TX : string := "DONTCARE";
    CH1_INVERT_TX : string := "DONTCARE";
    CH0_PRBS_SELECTION : string := "DONTCARE";
    CH1_PRBS_SELECTION : string := "DONTCARE";
    CH0_GE_AN_ENABLE : string := "DONTCARE";
    CH1_GE_AN_ENABLE : string := "DONTCARE";
    CH0_PRBS_LOCK : string := "DONTCARE";
    CH1_PRBS_LOCK : string := "DONTCARE";
    CH0_PRBS_ENABLE : string := "DONTCARE";
    CH1_PRBS_ENABLE : string := "DONTCARE";
    CH0_ENABLE_CG_ALIGN : string := "DONTCARE";
    CH1_ENABLE_CG_ALIGN : string := "DONTCARE";
    CH0_TX_GEAR_MODE : string := "DONTCARE";
    CH1_TX_GEAR_MODE : string := "DONTCARE";
    CH0_RX_GEAR_MODE : string := "DONTCARE";
    CH1_RX_GEAR_MODE : string := "DONTCARE";
    CH0_PCS_DET_TIME_SEL : string := "DONTCARE";
    CH1_PCS_DET_TIME_SEL : string := "DONTCARE";
    CH0_PCIE_EI_EN : string := "DONTCARE";
    CH1_PCIE_EI_EN : string := "DONTCARE";
    CH0_TX_GEAR_BYPASS : string := "DONTCARE";
    CH1_TX_GEAR_BYPASS : string := "DONTCARE";
    CH0_ENC_BYPASS : string := "DONTCARE";
    CH1_ENC_BYPASS : string := "DONTCARE";
    CH0_SB_BYPASS : string := "DONTCARE";
    CH1_SB_BYPASS : string := "DONTCARE";
    CH0_RX_SB_BYPASS : string := "DONTCARE";
    CH1_RX_SB_BYPASS : string := "DONTCARE";
    CH0_WA_BYPASS : string := "DONTCARE";
    CH1_WA_BYPASS : string := "DONTCARE";
    CH0_DEC_BYPASS : string := "DONTCARE";
    CH1_DEC_BYPASS : string := "DONTCARE";
    CH0_CTC_BYPASS : string := "DONTCARE";
    CH1_CTC_BYPASS : string := "DONTCARE";
    CH0_RX_GEAR_BYPASS : string := "DONTCARE";
    CH1_RX_GEAR_BYPASS : string := "DONTCARE";
    CH0_LSM_DISABLE : string := "DONTCARE";
    CH1_LSM_DISABLE : string := "DONTCARE";
    CH0_MATCH_2_ENABLE : string := "DONTCARE";
    CH1_MATCH_2_ENABLE : string := "DONTCARE";
    CH0_MATCH_4_ENABLE : string := "DONTCARE";
    CH1_MATCH_4_ENABLE : string := "DONTCARE";
    CH0_MIN_IPG_CNT : string := "DONTCARE";
    CH1_MIN_IPG_CNT : string := "DONTCARE";
    CH0_CC_MATCH_1 : string := "DONTCARE";
    CH1_CC_MATCH_1 : string := "DONTCARE";
    CH0_CC_MATCH_2 : string := "DONTCARE";
    CH1_CC_MATCH_2 : string := "DONTCARE";
    CH0_CC_MATCH_3 : string := "DONTCARE";
    CH1_CC_MATCH_3 : string := "DONTCARE";
    CH0_CC_MATCH_4 : string := "DONTCARE";
    CH1_CC_MATCH_4 : string := "DONTCARE";
    CH0_UDF_COMMA_MASK : string := "DONTCARE";
    CH1_UDF_COMMA_MASK : string := "DONTCARE";
    CH0_UDF_COMMA_A : string := "DONTCARE";
    CH1_UDF_COMMA_A : string := "DONTCARE";
    CH0_UDF_COMMA_B : string := "DONTCARE";
    CH1_UDF_COMMA_B : string := "DONTCARE";
    CH0_RX_DCO_CK_DIV : string := "DONTCARE";
    CH1_RX_DCO_CK_DIV : string := "DONTCARE";
    CH0_RCV_DCC_EN : string := "DONTCARE";
    CH1_RCV_DCC_EN : string := "DONTCARE";
    CH0_REQ_LVL_SET : string := "DONTCARE";
    CH1_REQ_LVL_SET : string := "DONTCARE";
    CH0_REQ_EN : string := "DONTCARE";
    CH1_REQ_EN : string := "DONTCARE";
    CH0_RTERM_RX : string := "DONTCARE";
    CH1_RTERM_RX : string := "DONTCARE";
    CH0_PDEN_SEL : string := "DONTCARE";
    CH1_PDEN_SEL : string := "DONTCARE";
    CH0_LDR_RX2CORE_SEL : string := "DONTCARE";
    CH1_LDR_RX2CORE_SEL : string := "DONTCARE";
    CH0_LDR_CORE2TX_SEL : string := "DONTCARE";
    CH1_LDR_CORE2TX_SEL : string := "DONTCARE";
    CH0_TPWDNB : string := "DONTCARE";
    CH1_TPWDNB : string := "DONTCARE";
    CH0_RATE_MODE_TX : string := "DONTCARE";
    CH1_RATE_MODE_TX : string := "DONTCARE";
    CH0_RTERM_TX : string := "DONTCARE";
    CH1_RTERM_TX : string := "DONTCARE";
    CH0_TX_CM_SEL : string := "DONTCARE";
    CH1_TX_CM_SEL : string := "DONTCARE";
    CH0_TDRV_PRE_EN : string := "DONTCARE";
    CH1_TDRV_PRE_EN : string := "DONTCARE";
    CH0_TDRV_SLICE0_SEL : string := "DONTCARE";
    CH1_TDRV_SLICE0_SEL : string := "DONTCARE";
    CH0_TDRV_SLICE1_SEL : string := "DONTCARE";
    CH1_TDRV_SLICE1_SEL : string := "DONTCARE";
    CH0_TDRV_SLICE2_SEL : string := "DONTCARE";
    CH1_TDRV_SLICE2_SEL : string := "DONTCARE";
    CH0_TDRV_SLICE3_SEL : string := "DONTCARE";
    CH1_TDRV_SLICE3_SEL : string := "DONTCARE";
    CH0_TDRV_SLICE4_SEL : string := "DONTCARE";
    CH1_TDRV_SLICE4_SEL : string := "DONTCARE";
    CH0_TDRV_SLICE5_SEL : string := "DONTCARE";
    CH1_TDRV_SLICE5_SEL : string := "DONTCARE";
    CH0_TDRV_SLICE0_CUR : string := "DONTCARE";
    CH1_TDRV_SLICE0_CUR : string := "DONTCARE";
    CH0_TDRV_SLICE1_CUR : string := "DONTCARE";
    CH1_TDRV_SLICE1_CUR : string := "DONTCARE";
    CH0_TDRV_SLICE2_CUR : string := "DONTCARE";
    CH1_TDRV_SLICE2_CUR : string := "DONTCARE";
    CH0_TDRV_SLICE3_CUR : string := "DONTCARE";
    CH1_TDRV_SLICE3_CUR : string := "DONTCARE";
    CH0_TDRV_SLICE4_CUR : string := "DONTCARE";
    CH1_TDRV_SLICE4_CUR : string := "DONTCARE";
    CH0_TDRV_SLICE5_CUR : string := "DONTCARE";
    CH1_TDRV_SLICE5_CUR : string := "DONTCARE";
    CH0_TDRV_DAT_SEL : string := "DONTCARE";
    CH1_TDRV_DAT_SEL : string := "DONTCARE";
    CH0_TX_DIV11_SEL : string := "DONTCARE";
    CH1_TX_DIV11_SEL : string := "DONTCARE";
    CH0_RPWDNB : string := "DONTCARE";
    CH1_RPWDNB : string := "DONTCARE";
    CH0_RATE_MODE_RX : string := "DONTCARE";
    CH1_RATE_MODE_RX : string := "DONTCARE";
    CH0_RLOS_SEL : string := "DONTCARE";
    CH1_RLOS_SEL : string := "DONTCARE";
    CH0_RX_LOS_LVL : string := "DONTCARE";
    CH1_RX_LOS_LVL : string := "DONTCARE";
    CH0_RX_LOS_CEQ : string := "DONTCARE";
    CH1_RX_LOS_CEQ : string := "DONTCARE";
    CH0_RX_LOS_HYST_EN : string := "DONTCARE";
    CH1_RX_LOS_HYST_EN : string := "DONTCARE";
    CH0_RX_LOS_EN : string := "DONTCARE";
    CH1_RX_LOS_EN : string := "DONTCARE";
    CH0_RX_DIV11_SEL : string := "DONTCARE";
    CH1_RX_DIV11_SEL : string := "DONTCARE";
    CH0_SEL_SD_RX_CLK : string := "DONTCARE";
    CH1_SEL_SD_RX_CLK : string := "DONTCARE";
    CH0_FF_RX_H_CLK_EN : string := "DONTCARE";
    CH1_FF_RX_H_CLK_EN : string := "DONTCARE";
    CH0_FF_RX_F_CLK_DIS : string := "DONTCARE";
    CH1_FF_RX_F_CLK_DIS : string := "DONTCARE";
    CH0_FF_TX_H_CLK_EN : string := "DONTCARE";
    CH1_FF_TX_H_CLK_EN : string := "DONTCARE";
    CH0_FF_TX_F_CLK_DIS : string := "DONTCARE";
    CH1_FF_TX_F_CLK_DIS : string := "DONTCARE";
    CH0_RX_RATE_SEL : string := "DONTCARE";
    CH1_RX_RATE_SEL : string := "DONTCARE";
    CH0_TDRV_POST_EN : string := "DONTCARE";
    CH1_TDRV_POST_EN : string := "DONTCARE";
    CH0_TX_POST_SIGN : string := "DONTCARE";
    CH1_TX_POST_SIGN : string := "DONTCARE";
    CH0_TX_PRE_SIGN : string := "DONTCARE";
    CH1_TX_PRE_SIGN : string := "DONTCARE";
    CH0_RXTERM_CM : string := "DONTCARE";
    CH1_RXTERM_CM : string := "DONTCARE";
    CH0_RXIN_CM : string := "DONTCARE";
    CH1_RXIN_CM : string := "DONTCARE";
    CH0_LEQ_OFFSET_SEL : string := "DONTCARE";
    CH1_LEQ_OFFSET_SEL : string := "DONTCARE";
    CH0_LEQ_OFFSET_TRIM : string := "DONTCARE";
    CH1_LEQ_OFFSET_TRIM : string := "DONTCARE";
    D_TX_MAX_RATE : string := "DONTCARE";
    CH0_CDR_MAX_RATE : string := "DONTCARE";
    CH1_CDR_MAX_RATE : string := "DONTCARE";
    CH0_TXAMPLITUDE : string := "DONTCARE";
    CH1_TXAMPLITUDE : string := "DONTCARE";
    CH0_TXDEPRE : string := "DONTCARE";
    CH1_TXDEPRE : string := "DONTCARE";
    CH0_TXDEPOST : string := "DONTCARE";
    CH1_TXDEPOST : string := "DONTCARE";
    CH0_PROTOCOL : string := "DONTCARE";
    CH1_PROTOCOL : string := "DONTCARE";
    D_ISETLOS : string := "DONTCARE";
    D_SETIRPOLY_AUX : string := "DONTCARE";
    D_SETICONST_AUX : string := "DONTCARE";
    D_SETIRPOLY_CH : string := "DONTCARE";
    D_SETICONST_CH : string := "DONTCARE";
    D_REQ_ISET : string := "DONTCARE";
    D_PD_ISET : string := "DONTCARE";
    D_DCO_CALIB_TIME_SEL : string := "DONTCARE";
    CH0_DCOCTLGI : string := "DONTCARE";
    CH1_DCOCTLGI : string := "DONTCARE";
    CH0_DCOATDDLY : string := "DONTCARE";
    CH1_DCOATDDLY : string := "DONTCARE";
    CH0_DCOATDCFG : string := "DONTCARE";
    CH1_DCOATDCFG : string := "DONTCARE";
    CH0_DCOBYPSATD : string := "DONTCARE";
    CH1_DCOBYPSATD : string := "DONTCARE";
    CH0_DCOSCALEI : string := "DONTCARE";
    CH1_DCOSCALEI : string := "DONTCARE";
    CH0_DCOITUNE4LSB : string := "DONTCARE";
    CH1_DCOITUNE4LSB : string := "DONTCARE";
    CH0_DCOIOSTUNE : string := "DONTCARE";
    CH1_DCOIOSTUNE : string := "DONTCARE";
    CH0_DCODISBDAVOID : string := "DONTCARE";
    CH1_DCODISBDAVOID : string := "DONTCARE";
    CH0_DCOCALDIV : string := "DONTCARE";
    CH1_DCOCALDIV : string := "DONTCARE";
    CH0_DCONUOFLSB : string := "DONTCARE";
    CH1_DCONUOFLSB : string := "DONTCARE";
    CH0_DCOIUPDNX2 : string := "DONTCARE";
    CH1_DCOIUPDNX2 : string := "DONTCARE";
    CH0_DCOSTEP : string := "DONTCARE";
    CH1_DCOSTEP : string := "DONTCARE";
    CH0_DCOSTARTVAL : string := "DONTCARE";
    CH1_DCOSTARTVAL : string := "DONTCARE";
    CH0_DCOFLTDAC : string := "DONTCARE";
    CH1_DCOFLTDAC : string := "DONTCARE";
    CH0_DCOITUNE : string := "DONTCARE";
    CH1_DCOITUNE : string := "DONTCARE";
    CH0_DCOFTNRG : string := "DONTCARE";
    CH1_DCOFTNRG : string := "DONTCARE";
    CH0_CDR_CNT4SEL : string := "DONTCARE";
    CH1_CDR_CNT4SEL : string := "DONTCARE";
    CH0_CDR_CNT8SEL : string := "DONTCARE";
    CH1_CDR_CNT8SEL : string := "DONTCARE";
    CH0_BAND_THRESHOLD : string := "DONTCARE";
    CH1_BAND_THRESHOLD : string := "DONTCARE";
    CH0_AUTO_FACQ_EN : string := "DONTCARE";
    CH1_AUTO_FACQ_EN : string := "DONTCARE";
    CH0_AUTO_CALIB_EN : string := "DONTCARE";
    CH1_AUTO_CALIB_EN : string := "DONTCARE";
    CH0_CALIB_CK_MODE : string := "DONTCARE";
    CH1_CALIB_CK_MODE : string := "DONTCARE";
    CH0_REG_BAND_OFFSET : string := "DONTCARE";
    CH1_REG_BAND_OFFSET : string := "DONTCARE";
    CH0_REG_BAND_SEL : string := "DONTCARE";
    CH1_REG_BAND_SEL : string := "DONTCARE";
    CH0_REG_IDAC_SEL : string := "DONTCARE";
    CH1_REG_IDAC_SEL : string := "DONTCARE";
    CH0_REG_IDAC_EN : string := "DONTCARE";
    CH1_REG_IDAC_EN : string := "DONTCARE";
    D_TXPLL_PWDNB : string := "DONTCARE";
    D_SETPLLRC : string := "DONTCARE";
    D_REFCK_MODE : string := "DONTCARE";
    D_TX_VCO_CK_DIV : string := "DONTCARE";
    D_PLL_LOL_SET : string := "DONTCARE";
    D_RG_EN : string := "DONTCARE";
    D_RG_SET : string := "DONTCARE";
    D_CMUSETISCL4VCO : string := "DONTCARE";
    D_CMUSETI4VCO : string := "DONTCARE";
    D_CMUSETINITVCT : string := "DONTCARE";
    D_CMUSETZGM : string := "DONTCARE";
    D_CMUSETP2AGM : string := "DONTCARE";
    D_CMUSETP1GM : string := "DONTCARE";
    D_CMUSETI4CPZ : string := "DONTCARE";
    D_CMUSETI4CPP : string := "DONTCARE";
    D_CMUSETICP4Z : string := "DONTCARE";
    D_CMUSETICP4P : string := "DONTCARE";
    D_CMUSETBIASI : string := "DONTCARE"  );
  port (
    CH0_HDINP :   in  std_logic;
    CH1_HDINP :   in  std_logic;
    CH0_HDINN :   in  std_logic;
    CH1_HDINN :   in  std_logic;
    D_TXBIT_CLKP_FROM_ND :   in  std_logic;
    D_TXBIT_CLKN_FROM_ND :   in  std_logic;
    D_SYNC_ND :   in  std_logic;
    D_TXPLL_LOL_FROM_ND :   in  std_logic;
    CH0_RX_REFCLK :   in  std_logic;
    CH1_RX_REFCLK :   in  std_logic;
    CH0_FF_RXI_CLK :   in  std_logic;
    CH1_FF_RXI_CLK :   in  std_logic;
    CH0_FF_TXI_CLK :   in  std_logic;
    CH1_FF_TXI_CLK :   in  std_logic;
    CH0_FF_EBRD_CLK :   in  std_logic;
    CH1_FF_EBRD_CLK :   in  std_logic;
    CH0_FF_TX_D_0 :   in  std_logic;
    CH1_FF_TX_D_0 :   in  std_logic;
    CH0_FF_TX_D_1 :   in  std_logic;
    CH1_FF_TX_D_1 :   in  std_logic;
    CH0_FF_TX_D_2 :   in  std_logic;
    CH1_FF_TX_D_2 :   in  std_logic;
    CH0_FF_TX_D_3 :   in  std_logic;
    CH1_FF_TX_D_3 :   in  std_logic;
    CH0_FF_TX_D_4 :   in  std_logic;
    CH1_FF_TX_D_4 :   in  std_logic;
    CH0_FF_TX_D_5 :   in  std_logic;
    CH1_FF_TX_D_5 :   in  std_logic;
    CH0_FF_TX_D_6 :   in  std_logic;
    CH1_FF_TX_D_6 :   in  std_logic;
    CH0_FF_TX_D_7 :   in  std_logic;
    CH1_FF_TX_D_7 :   in  std_logic;
    CH0_FF_TX_D_8 :   in  std_logic;
    CH1_FF_TX_D_8 :   in  std_logic;
    CH0_FF_TX_D_9 :   in  std_logic;
    CH1_FF_TX_D_9 :   in  std_logic;
    CH0_FF_TX_D_10 :   in  std_logic;
    CH1_FF_TX_D_10 :   in  std_logic;
    CH0_FF_TX_D_11 :   in  std_logic;
    CH1_FF_TX_D_11 :   in  std_logic;
    CH0_FF_TX_D_12 :   in  std_logic;
    CH1_FF_TX_D_12 :   in  std_logic;
    CH0_FF_TX_D_13 :   in  std_logic;
    CH1_FF_TX_D_13 :   in  std_logic;
    CH0_FF_TX_D_14 :   in  std_logic;
    CH1_FF_TX_D_14 :   in  std_logic;
    CH0_FF_TX_D_15 :   in  std_logic;
    CH1_FF_TX_D_15 :   in  std_logic;
    CH0_FF_TX_D_16 :   in  std_logic;
    CH1_FF_TX_D_16 :   in  std_logic;
    CH0_FF_TX_D_17 :   in  std_logic;
    CH1_FF_TX_D_17 :   in  std_logic;
    CH0_FF_TX_D_18 :   in  std_logic;
    CH1_FF_TX_D_18 :   in  std_logic;
    CH0_FF_TX_D_19 :   in  std_logic;
    CH1_FF_TX_D_19 :   in  std_logic;
    CH0_FF_TX_D_20 :   in  std_logic;
    CH1_FF_TX_D_20 :   in  std_logic;
    CH0_FF_TX_D_21 :   in  std_logic;
    CH1_FF_TX_D_21 :   in  std_logic;
    CH0_FF_TX_D_22 :   in  std_logic;
    CH1_FF_TX_D_22 :   in  std_logic;
    CH0_FF_TX_D_23 :   in  std_logic;
    CH1_FF_TX_D_23 :   in  std_logic;
    CH0_FFC_EI_EN :   in  std_logic;
    CH1_FFC_EI_EN :   in  std_logic;
    CH0_FFC_PCIE_DET_EN :   in  std_logic;
    CH1_FFC_PCIE_DET_EN :   in  std_logic;
    CH0_FFC_PCIE_CT :   in  std_logic;
    CH1_FFC_PCIE_CT :   in  std_logic;
    CH0_FFC_SB_INV_RX :   in  std_logic;
    CH1_FFC_SB_INV_RX :   in  std_logic;
    CH0_FFC_ENABLE_CGALIGN :   in  std_logic;
    CH1_FFC_ENABLE_CGALIGN :   in  std_logic;
    CH0_FFC_SIGNAL_DETECT :   in  std_logic;
    CH1_FFC_SIGNAL_DETECT :   in  std_logic;
    CH0_FFC_FB_LOOPBACK :   in  std_logic;
    CH1_FFC_FB_LOOPBACK :   in  std_logic;
    CH0_FFC_SB_PFIFO_LP :   in  std_logic;
    CH1_FFC_SB_PFIFO_LP :   in  std_logic;
    CH0_FFC_PFIFO_CLR :   in  std_logic;
    CH1_FFC_PFIFO_CLR :   in  std_logic;
    CH0_FFC_RATE_MODE_RX :   in  std_logic;
    CH1_FFC_RATE_MODE_RX :   in  std_logic;
    CH0_FFC_RATE_MODE_TX :   in  std_logic;
    CH1_FFC_RATE_MODE_TX :   in  std_logic;
    CH0_FFC_DIV11_MODE_RX :   in  std_logic;
    CH1_FFC_DIV11_MODE_RX :   in  std_logic;
    CH0_FFC_RX_GEAR_MODE :   in  std_logic;
    CH1_FFC_RX_GEAR_MODE :   in  std_logic;
    CH0_FFC_TX_GEAR_MODE :   in  std_logic;
    CH1_FFC_TX_GEAR_MODE :   in  std_logic;
    CH0_FFC_DIV11_MODE_TX :   in  std_logic;
    CH1_FFC_DIV11_MODE_TX :   in  std_logic;
    CH0_FFC_LDR_CORE2TX_EN :   in  std_logic;
    CH1_FFC_LDR_CORE2TX_EN :   in  std_logic;
    CH0_FFC_LANE_TX_RST :   in  std_logic;
    CH1_FFC_LANE_TX_RST :   in  std_logic;
    CH0_FFC_LANE_RX_RST :   in  std_logic;
    CH1_FFC_LANE_RX_RST :   in  std_logic;
    CH0_FFC_RRST :   in  std_logic;
    CH1_FFC_RRST :   in  std_logic;
    CH0_FFC_TXPWDNB :   in  std_logic;
    CH1_FFC_TXPWDNB :   in  std_logic;
    CH0_FFC_RXPWDNB :   in  std_logic;
    CH1_FFC_RXPWDNB :   in  std_logic;
    CH0_LDR_CORE2TX :   in  std_logic;
    CH1_LDR_CORE2TX :   in  std_logic;
    D_SCIWDATA0 :   in  std_logic;
    D_SCIWDATA1 :   in  std_logic;
    D_SCIWDATA2 :   in  std_logic;
    D_SCIWDATA3 :   in  std_logic;
    D_SCIWDATA4 :   in  std_logic;
    D_SCIWDATA5 :   in  std_logic;
    D_SCIWDATA6 :   in  std_logic;
    D_SCIWDATA7 :   in  std_logic;
    D_SCIADDR0 :   in  std_logic;
    D_SCIADDR1 :   in  std_logic;
    D_SCIADDR2 :   in  std_logic;
    D_SCIADDR3 :   in  std_logic;
    D_SCIADDR4 :   in  std_logic;
    D_SCIADDR5 :   in  std_logic;
    D_SCIENAUX :   in  std_logic;
    D_SCISELAUX :   in  std_logic;
    CH0_SCIEN :   in  std_logic;
    CH1_SCIEN :   in  std_logic;
    CH0_SCISEL :   in  std_logic;
    CH1_SCISEL :   in  std_logic;
    D_SCIRD :   in  std_logic;
    D_SCIWSTN :   in  std_logic;
    D_CYAWSTN :   in  std_logic;
    D_FFC_SYNC_TOGGLE :   in  std_logic;
    D_FFC_DUAL_RST :   in  std_logic;
    D_FFC_MACRO_RST :   in  std_logic;
    D_FFC_MACROPDB :   in  std_logic;
    D_FFC_TRST :   in  std_logic;
    CH0_FFC_CDR_EN_BITSLIP :   in  std_logic;
    CH1_FFC_CDR_EN_BITSLIP :   in  std_logic;
    D_SCAN_ENABLE :   in  std_logic;
    D_SCAN_IN_0 :   in  std_logic;
    D_SCAN_IN_1 :   in  std_logic;
    D_SCAN_IN_2 :   in  std_logic;
    D_SCAN_IN_3 :   in  std_logic;
    D_SCAN_IN_4 :   in  std_logic;
    D_SCAN_IN_5 :   in  std_logic;
    D_SCAN_IN_6 :   in  std_logic;
    D_SCAN_IN_7 :   in  std_logic;
    D_SCAN_MODE :   in  std_logic;
    D_SCAN_RESET :   in  std_logic;
    D_CIN0 :   in  std_logic;
    D_CIN1 :   in  std_logic;
    D_CIN2 :   in  std_logic;
    D_CIN3 :   in  std_logic;
    D_CIN4 :   in  std_logic;
    D_CIN5 :   in  std_logic;
    D_CIN6 :   in  std_logic;
    D_CIN7 :   in  std_logic;
    D_CIN8 :   in  std_logic;
    D_CIN9 :   in  std_logic;
    D_CIN10 :   in  std_logic;
    D_CIN11 :   in  std_logic;
    CH0_HDOUTP :   out  std_logic;
    CH1_HDOUTP :   out  std_logic;
    CH0_HDOUTN :   out  std_logic;
    CH1_HDOUTN :   out  std_logic;
    D_TXBIT_CLKP_TO_ND :   out  std_logic;
    D_TXBIT_CLKN_TO_ND :   out  std_logic;
    D_SYNC_PULSE2ND :   out  std_logic;
    D_TXPLL_LOL_TO_ND :   out  std_logic;
    CH0_FF_RX_F_CLK :   out  std_logic;
    CH1_FF_RX_F_CLK :   out  std_logic;
    CH0_FF_RX_H_CLK :   out  std_logic;
    CH1_FF_RX_H_CLK :   out  std_logic;
    CH0_FF_TX_F_CLK :   out  std_logic;
    CH1_FF_TX_F_CLK :   out  std_logic;
    CH0_FF_TX_H_CLK :   out  std_logic;
    CH1_FF_TX_H_CLK :   out  std_logic;
    CH0_FF_RX_PCLK :   out  std_logic;
    CH1_FF_RX_PCLK :   out  std_logic;
    CH0_FF_TX_PCLK :   out  std_logic;
    CH1_FF_TX_PCLK :   out  std_logic;
    CH0_FF_RX_D_0 :   out  std_logic;
    CH1_FF_RX_D_0 :   out  std_logic;
    CH0_FF_RX_D_1 :   out  std_logic;
    CH1_FF_RX_D_1 :   out  std_logic;
    CH0_FF_RX_D_2 :   out  std_logic;
    CH1_FF_RX_D_2 :   out  std_logic;
    CH0_FF_RX_D_3 :   out  std_logic;
    CH1_FF_RX_D_3 :   out  std_logic;
    CH0_FF_RX_D_4 :   out  std_logic;
    CH1_FF_RX_D_4 :   out  std_logic;
    CH0_FF_RX_D_5 :   out  std_logic;
    CH1_FF_RX_D_5 :   out  std_logic;
    CH0_FF_RX_D_6 :   out  std_logic;
    CH1_FF_RX_D_6 :   out  std_logic;
    CH0_FF_RX_D_7 :   out  std_logic;
    CH1_FF_RX_D_7 :   out  std_logic;
    CH0_FF_RX_D_8 :   out  std_logic;
    CH1_FF_RX_D_8 :   out  std_logic;
    CH0_FF_RX_D_9 :   out  std_logic;
    CH1_FF_RX_D_9 :   out  std_logic;
    CH0_FF_RX_D_10 :   out  std_logic;
    CH1_FF_RX_D_10 :   out  std_logic;
    CH0_FF_RX_D_11 :   out  std_logic;
    CH1_FF_RX_D_11 :   out  std_logic;
    CH0_FF_RX_D_12 :   out  std_logic;
    CH1_FF_RX_D_12 :   out  std_logic;
    CH0_FF_RX_D_13 :   out  std_logic;
    CH1_FF_RX_D_13 :   out  std_logic;
    CH0_FF_RX_D_14 :   out  std_logic;
    CH1_FF_RX_D_14 :   out  std_logic;
    CH0_FF_RX_D_15 :   out  std_logic;
    CH1_FF_RX_D_15 :   out  std_logic;
    CH0_FF_RX_D_16 :   out  std_logic;
    CH1_FF_RX_D_16 :   out  std_logic;
    CH0_FF_RX_D_17 :   out  std_logic;
    CH1_FF_RX_D_17 :   out  std_logic;
    CH0_FF_RX_D_18 :   out  std_logic;
    CH1_FF_RX_D_18 :   out  std_logic;
    CH0_FF_RX_D_19 :   out  std_logic;
    CH1_FF_RX_D_19 :   out  std_logic;
    CH0_FF_RX_D_20 :   out  std_logic;
    CH1_FF_RX_D_20 :   out  std_logic;
    CH0_FF_RX_D_21 :   out  std_logic;
    CH1_FF_RX_D_21 :   out  std_logic;
    CH0_FF_RX_D_22 :   out  std_logic;
    CH1_FF_RX_D_22 :   out  std_logic;
    CH0_FF_RX_D_23 :   out  std_logic;
    CH1_FF_RX_D_23 :   out  std_logic;
    CH0_FFS_PCIE_DONE :   out  std_logic;
    CH1_FFS_PCIE_DONE :   out  std_logic;
    CH0_FFS_PCIE_CON :   out  std_logic;
    CH1_FFS_PCIE_CON :   out  std_logic;
    CH0_FFS_RLOS :   out  std_logic;
    CH1_FFS_RLOS :   out  std_logic;
    CH0_FFS_LS_SYNC_STATUS :   out  std_logic;
    CH1_FFS_LS_SYNC_STATUS :   out  std_logic;
    CH0_FFS_CC_UNDERRUN :   out  std_logic;
    CH1_FFS_CC_UNDERRUN :   out  std_logic;
    CH0_FFS_CC_OVERRUN :   out  std_logic;
    CH1_FFS_CC_OVERRUN :   out  std_logic;
    CH0_FFS_RXFBFIFO_ERROR :   out  std_logic;
    CH1_FFS_RXFBFIFO_ERROR :   out  std_logic;
    CH0_FFS_TXFBFIFO_ERROR :   out  std_logic;
    CH1_FFS_TXFBFIFO_ERROR :   out  std_logic;
    CH0_FFS_RLOL :   out  std_logic;
    CH1_FFS_RLOL :   out  std_logic;
    CH0_FFS_SKP_ADDED :   out  std_logic;
    CH1_FFS_SKP_ADDED :   out  std_logic;
    CH0_FFS_SKP_DELETED :   out  std_logic;
    CH1_FFS_SKP_DELETED :   out  std_logic;
    CH0_LDR_RX2CORE :   out  std_logic;
    CH1_LDR_RX2CORE :   out  std_logic;
    D_SCIRDATA0 :   out  std_logic;
    D_SCIRDATA1 :   out  std_logic;
    D_SCIRDATA2 :   out  std_logic;
    D_SCIRDATA3 :   out  std_logic;
    D_SCIRDATA4 :   out  std_logic;
    D_SCIRDATA5 :   out  std_logic;
    D_SCIRDATA6 :   out  std_logic;
    D_SCIRDATA7 :   out  std_logic;
    D_SCIINT :   out  std_logic;
    D_SCAN_OUT_0 :   out  std_logic;
    D_SCAN_OUT_1 :   out  std_logic;
    D_SCAN_OUT_2 :   out  std_logic;
    D_SCAN_OUT_3 :   out  std_logic;
    D_SCAN_OUT_4 :   out  std_logic;
    D_SCAN_OUT_5 :   out  std_logic;
    D_SCAN_OUT_6 :   out  std_logic;
    D_SCAN_OUT_7 :   out  std_logic;
    D_COUT0 :   out  std_logic;
    D_COUT1 :   out  std_logic;
    D_COUT2 :   out  std_logic;
    D_COUT3 :   out  std_logic;
    D_COUT4 :   out  std_logic;
    D_COUT5 :   out  std_logic;
    D_COUT6 :   out  std_logic;
    D_COUT7 :   out  std_logic;
    D_COUT8 :   out  std_logic;
    D_COUT9 :   out  std_logic;
    D_COUT10 :   out  std_logic;
    D_COUT11 :   out  std_logic;
    D_COUT12 :   out  std_logic;
    D_COUT13 :   out  std_logic;
    D_COUT14 :   out  std_logic;
    D_COUT15 :   out  std_logic;
    D_COUT16 :   out  std_logic;
    D_COUT17 :   out  std_logic;
    D_COUT18 :   out  std_logic;
    D_COUT19 :   out  std_logic;
    D_REFCLKI :   in  std_logic;
    D_FFS_PLOL :   out  std_logic  );
end component;

end package;
