/* SPDX-License-Identifier: BSD-3-Clause */
/*
 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
 */

#ifndef RAMBLUR_PIMEM_HWIO_H
#define RAMBLUR_PIMEM_HWIO_H

/*
 * Minimal HWIO definitions required by ramblur_pimem_v3.c.
 *
 * NOTE: The autogenerated-style *_INI() macros rely on helper functions
 * (e.g. in_dword_masked()) provided by the including C file.
 */

#define RAMBLUR_PIMEM_REG_SIZE			0x4000

/*
 * RAMBLUR_VERSION: PIMEM Version Details
 *
 * [bits]  [value]
 * 31:24   MAJOR_VERSION
 * 23:16   MINOR_VERSION
 * 15:0    STEP_VERSION
 */
#define RAMBLUR_VERSION_MAJOR_BMSK	0xff000000
#define RAMBLUR_VERSION_MINOR_BMSK	0x00ff0000
#define RAMBLUR_VERSION_STEP_BMSK	0x0000ffff
#define RAMBLUR_VERSION_MAJOR_SHFT	0x18
#define RAMBLUR_VERSION_MINOR_SHFT	0x10
#define RAMBLUR_VERSION_STEP_SHFT	0x0
#define RAMBLUR_VERSION_ADDR_OFFSET	0x00000000
#define RAMBLUR_VERSION_ADDR		(RAMBLUR_VERSION_ADDR_OFFSET)

/* RAMBLUR_WINn_ALGORITHM_CONFIG (n=[0..3]) */
#define RAMBLUR_WINn_ALGORITHM_CONFIG_ADDR_OFFSET(n)	(0x68 + (0x4 * (n)))
#define RAMBLUR_WINn_ALGORITHM_CONFIG_ADDR(n)		\
	(RAMBLUR_WINn_ALGORITHM_CONFIG_ADDR_OFFSET(n))

/* Security attributes position in ALGORITHM_CONFIG register */
#define RAMBLUR_WIN0_ALGORITHM_CONFIDENTIALITY_ENABLE_SHFT	0x2
#define RAMBLUR_WIN0_ALGORITHM_INTEGRITY_ENABLE_SHFT		0x1
#define RAMBLUR_WIN0_ALGORITHM_ANTIROLLBACK_ENABLE_SHFT		0x0

/* RAMBLUR_WINn_SIZE (n=[0..3]) */
#define RAMBLUR_WINn_SIZE_RMSK			0x07f00000
#define RAMBLUR_WINn_SIZE_ADDR_OFFSET(n)	(0x58 + (0x4 * (n)))
#define RAMBLUR_WINn_SIZE_ADDR(n)	(RAMBLUR_WINn_SIZE_ADDR_OFFSET(n))

/* RAMBLUR_WINn_CTL, n=[0..3] */
#define RAMBLUR_WINn_CTL_OFFSET(n)		(0x78 + (0x4 * (n)))
#define RAMBLUR_WINn_CTL_ADDR(n)		(RAMBLUR_WINn_CTL_OFFSET(n))
#define RAMBLUR_WINn_CTL_RMSK			0xf
#define RAMBLUR_WINn_CTL_START_HW_INIT_BMSK	0x8
#define RAMBLUR_WINn_CTL_START_HW_INIT_SHFT	0x3
#define RAMBLUR_WINn_CTL_SW_INIT_MODE_BMSK	0x4
#define RAMBLUR_WINn_CTL_SW_INIT_MODE_SHFT	0x2
#define RAMBLUR_WINn_CTL_WIN_ENABLE_BMSK	0x2
#define RAMBLUR_WINn_CTL_WIN_ENABLE_SHFT	0x1
#define RAMBLUR_WINn_CTL_WIN_DISABLE_BMSK	0x1
#define RAMBLUR_WINn_CTL_WIN_DISABLE_SHFT	0x0
#define RAMBLUR_WINn_CTL_INI(n)			\
	in_dword_masked(RAMBLUR_WINn_CTL_ADDR(n), RAMBLUR_WINn_CTL_RMSK)

/* RAMBLUR_WINn_STATUS, n=[0..3] */
#define RAMBLUR_WINn_STATUS_OFFSET(n)		(0x98 + (0x4 * (n)))
#define RAMBLUR_WINn_STATUS_ADDR(n)		(RAMBLUR_WINn_STATUS_OFFSET(n))
#define RAMBLUR_WINn_STATUS_HW_INIT_DONE_BMSK		0x4
#define RAMBLUR_WINn_STATUS_HW_INIT_DONE_SHFT		0x2
#define RAMBLUR_WINn_STATUS_HW_INIT_IN_PROGRESS_BMSK	0x2
#define RAMBLUR_WINn_STATUS_HW_INIT_IN_PROGRESS_SHFT	0x1
#define RAMBLUR_WINn_STATUS_WIN_ENABLE_STATUS_BMSK	0x1
#define RAMBLUR_WINn_STATUS_WIN_ENABLE_STATUS_SHFT	0x0

/* RAMBLUR_WINn_HW_INIT_START, n=[0..3] */
#define RAMBLUR_WINn_HW_INIT_START_OFFSET(n)		(0x88 + (0x4 * (n)))
#define RAMBLUR_WINn_HW_INIT_START_ADDR(n)		\
	(RAMBLUR_WINn_HW_INIT_START_OFFSET(n))
#define RAMBLUR_WINn_HW_INIT_START_RMSK			0x3ff8000U
#define RAMBLUR_WINn_HW_INIT_START_BMSK			0x3ff8000U
#define RAMBLUR_WINn_HW_INIT_START_INI(n)			\
	in_dword_masked(RAMBLUR_WINn_HW_INIT_START_ADDR(n),	\
			RAMBLUR_WINn_HW_INIT_START_RMSK)

/* RAMBLUR_WINn_DATA_VAULT_ADDR_{HI,LOW}, n=[0..3] */
#define RAMBLUR_WINn_DATA_VAULT_ADDR_HI_RMSK		0xf
#define RAMBLUR_WINn_DATA_VAULT_ADDR_HI_OFFSET(n)	(0x38 + (0x4 * (n)))
#define RAMBLUR_WINn_DATA_VAULT_ADDR_HI_ADDR(n)		\
	(RAMBLUR_WINn_DATA_VAULT_ADDR_HI_OFFSET(n))
#define RAMBLUR_WINn_DATA_VAULT_ADDR_LOW_RMSK		0xfff00000
#define RAMBLUR_WINn_DATA_VAULT_ADDR_LOW_OFFSET(n)	(0x48 + (0x4 * (n)))
#define RAMBLUR_WINn_DATA_VAULT_ADDR_LOW_ADDR(n)	\
	(RAMBLUR_WINn_DATA_VAULT_ADDR_LOW_OFFSET(n))

/* RAMBLUR_WINn_DATA_TXN_QSB_CTL, n=[0..3] */
#define RAMBLUR_WINn_DATA_TXN_QSB_CTL_OFFSET(n)		(0xa8 + (0x4 * (n)))
#define RAMBLUR_WINn_DATA_TXN_QSB_CTL_ADDR(n)		\
	(RAMBLUR_WINn_DATA_TXN_QSB_CTL_OFFSET(n))
#define RAMBLUR_WINn_DATA_TXN_QSB_CTL_RMSK			0x0fffffff
#define RAMBLUR_WINn_DATA_TXN_QSB_CTL_AINNERCACHEABLE_BMSK	0x4000
#define RAMBLUR_WINn_DATA_TXN_QSB_CTL_AINNERCACHEABLE_SHFT	0xe
#define RAMBLUR_WINn_DATA_TXN_QSB_CTL_INI(n)			\
	in_dword_masked(RAMBLUR_WINn_DATA_TXN_QSB_CTL_ADDR(n),	\
			RAMBLUR_WINn_DATA_TXN_QSB_CTL_RMSK)

/* RAMBLUR_WINn_OVERHEAD_TXN_QSB_CTL, n=[0..3] */
#define RAMBLUR_WINn_OVERHEAD_TXN_QSB_CTL_OFFSET(n)	(0xb8 + (0x4 * (n)))
#define RAMBLUR_WINn_OVERHEAD_TXN_QSB_CTL_ADDR(n)	\
	(RAMBLUR_WINn_OVERHEAD_TXN_QSB_CTL_OFFSET(n))
#define RAMBLUR_WINn_OVERHEAD_TXN_QSB_CTL_RMSK			0x0fffffff
#define RAMBLUR_WINn_OVERHEAD_TXN_QSB_CTL_AINNERCACHEABLE_BMSK  0x4000
#define RAMBLUR_WINn_OVERHEAD_TXN_QSB_CTL_AINNERCACHEABLE_SHFT  0xe
#define RAMBLUR_WINn_OVERHEAD_TXN_QSB_CTL_INI(n)			\
	in_dword_masked(RAMBLUR_WINn_OVERHEAD_TXN_QSB_CTL_ADDR(n),	\
			RAMBLUR_WINn_OVERHEAD_TXN_QSB_CTL_RMSK)

#endif /* RAMBLUR_PIMEM_HWIO_H */
