VisionEgg.DaqLPT.LPTInput

Package VisionEgg :: Module DaqLPT :: Class LPTInput |
[frames] | no frames]

# Class LPTInput

source code

             object --+
                      |
    ClassWithParameters --+
                          |
      Daq.ChannelParameters --+
                              |
              Daq.Functionality --+
                                  |
                          Daq.Input --+
                                      |
                                     LPTInput

Instance Methods
get_data(self) Get status bits 0-7 of the LPT port. | source code
Inherited from `Daq.Functionality`: `__init__` Inherited from `ClassWithParameters`: `__getstate__`, `__setstate__`, `get_specified_type`, `is_constant_parameter`, `set`, `verify_parameters` Inherited from `object`: `__delattr__`, `__getattribute__`, `__hash__`, `__new__`, `__reduce__`, `__reduce_ex__`, `__repr__`, `__setattr__`, `__str__`

Class Variables
Inherited from `ClassWithParameters`: `__safe_for_unpickling__`, `constant_parameters_and_defaults`, `parameters_and_defaults`

Properties
Inherited from `object`: `__class__`

Method Details

### get_data(self) | source code
    Get status bits 0-7 of the LPT port.

    The status bits were not meant for high speed digital input.
    Nevertheless, for sampling one or two digital inputs at slow
    rates, they work fine.

    Bits 4 and 5 (pins 13 and 12, respectively) should be first
    choice to sample a digital voltage.  The other bits have some
    oddities. Bits 0 and 1 are designated reserved. Others are
    "active low"; they show a logic 0 when +5v is applied.

    bit3 = value & 0x08
    bit4 = value & 0x10
    bit5 = value & 0x20
    bit6 = value & 0x40
Overrides: Daq.Input.get_data